Energy-efficient design methodologies: High-performance VLSI adders

BR Zeydel, D Baran… - IEEE Journal of solid-state …, 2010 - ieeexplore.ieee.org
Energy-efficient design requires exploration of available algorithms, recurrence structures,
energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In …

Parasitic capacitance analysis of three-independent-gate field-effect transistors

P Cadareanu, J Romero-Gonzalez… - IEEE Journal of the …, 2021 - ieeexplore.ieee.org
Three-Independent-Gate Field-Effect Transistors (TIGFETs) are a promising alternative
technology that aims to replace or complement CMOS at advanced technology nodes. In this …

BCB evaluation of high-performance and low-leakage three-independent-gate field-effect transistors

J Romero-Gonzalez… - IEEE Journal on …, 2018 - ieeexplore.ieee.org
Three-independent-gate field-effect transistors (TIGFETs) are a promising next-generation
device technology. Their controllable-polarity capability allows for superior design of …

Analysis of switching activity in various implementation of combinational circuit

SA Pon, V Jeyalakshmi - 2020 6th International Conference on …, 2020 - ieeexplore.ieee.org
Low power technology emerges with increasing transistor count in a miniaturized silicon
chip. Power optimization in technology, circuit, layout, logic, architecture and algorithmic …

Comparison of performance of high speed VLSI adders

AN Jayanthi, CS Ravichandran - … International Conference on …, 2013 - ieeexplore.ieee.org
In modern VLSI design, the occurrence of delays is predictable. Many digital systems that
process data may have delays. Design requires thorough understanding of algorithms …

A systematic design of novel energy efficient 64 bit parallel prefix adder

N Jagadeeshkumar - 2021 - shodhganga.inflibnet.ac.in
The very large scale integration technology (VLSI) is extensively used in the most of the
emerging field like telecommunication, signal processing, consumer electronics and …

System-level analysis of graphene klein tunneling device

Y Yang, K Brenner, R Murali - 2011 11th IEEE International …, 2011 - ieeexplore.ieee.org
We analyze the system-level performance of graphene-based arithmetic logic units (ALUs)
enabled by Klein tunneling. Although the proposed graphene device is idealized (many …

A quick method for energy optimized gate sizing of digital circuits

M Aktan, D Baran, VG Oklobdzija - … Circuit and System Design. Power and …, 2011 - Springer
Exploration of energy & delay trade-offs requires a sizing solution for minimal energy under
operating delay and output load constraints. In this work, a simple method called Constant …

[HTML][HTML] Estimación de la actividad de conmutación en circuitos digitales CMOS VLSI

MCB Oliva - 2012 - dialnet.unirioja.es
La investigación que se ha desarrollado en esta Tesis se centra en el análisis de la
actividad de conmutación real durante la operación de circuitos combinacionales CMOS …

[图书][B] Energy and delay trade-offs in arithmetic circuits: Methodologies and optimizations

D Baran - 2011 - search.proquest.com
Technology scaling cannot provide sufficient amount of energy reduction to keep control of
the energy consumption of the current VLSI systems. In order to solve the problem of the …