The ability to estimate power consumption during early-stage definition and trade-off studies
is a key new methodology enhancement. Opportunities for saving power can be exposed via …

This paper presents core fusion, a reconfigurable chip multiprocessor (CMP) architecture
where groups of fundamentally independent cores can dynamically morph into a larger …

The issue logic of a dynamically-scheduled superscalar processor is a complex mechanism
devoted to start the execution of multiple instructions every cycle. Due to its complexity, it is …

Radio-frequency identification (RFID) as an emerging technology has generated enormous
amount of interest in the supply chain arena. With RFID technology, inventory can be tracked …

We apply a scalable approach for practical, comprehensive design space evaluation and
optimization. This approach combines design space sampling and statistical inference to …

This paper explores the multi-dimensional design space for chip multiprocessors, exploring
the inter-related variables of core count, pipeline depth, superscalar width, L2 cache size …

During the concept phase and definition of next generation high-end processors, power and
performance will need to be weighted appropriately to deliver competitive cost/performance …

Multiported register files are a critical component of high-performance superscalar
microprocessors. Conventional multiported structures can consume significant power and …

The anticipated explosive growth of pervasive and mobile computing devices that are
typically constrained by energy has brought hardware and software techniques for energy …

There is arguably no field in greater need of a comprehensive handbook than computer
engineering. The unparalleled rate of technological advancement, the explosion of …