The system-in-package (SiP) has gained much interest in the current rapid development of
integrated circuits (ICs) due to its advantages of integration, shrinking, and high density. This …

Abstract Three-dimensional (3D) integration is considered an effective approach to extend
and expand Moore's Law. Among them, Through-Silicon Via (TSV) technology provides …

This work focuses on the effect of Cu protrusion on the reliability of High Bandwidth Memory
(HBM) fabricated by wafer-to-wafer hybrid bonding (W2W-HB) process. The thermal stress …

Abstract Three-dimensional (3D) integrated packaging technology is gradually moving from
the laboratory to the market. Through silicon via (TSV) is the most critical structural unit in 3D …

Copper filled through silicon via (TSV-Cu) is a crucial technology for chip stacking and three-
dimensional (3D) vertical packaging. The multiple thermal loadings caused by the annealing …

Abstract The three-dimensional (3D) integrated packaging technology based on through-
silicon-via (TSV) is recognized as a new packaging technology which is most likely to …

Mixed-dimensional nanomaterials composed of one-dimensional (1D) and two-dimensional
(2D) nanomaterials, such as graphene–silver nanowire (AgNW) composite sandwiched …

The anisotropy property of silicon is a basic property which has been discussed widely in the
reliability assessment of electronic components. However, the effect of silicon anisotropy on …

The damage of the package structure, caused by the multi-stress coupling of various
environmental factors, can lead to the failure of the electronic device. Therefore, through the …

In this paper, the residual stresses with a nanoscale depth resolution at TSV-Cu/TiW/SiO2/Si
interfaces under different thermal loadings are characterized using the ion-beam layer …