Multigrain parallel processing on compiler cooperative chip multiprocessor

K Kimura, Y Wada, H Nakano, T Kodaka… - … Annual Workshop on …, 2005 - ieeexplore.ieee.org
This paper describes multigrain parallel processing on a compiler cooperative chip
multiprocessor. The multigrain parallel processing hierarchically exploits multiple grains of …

Compiler control power saving scheme for multi core processors

J Shirako, N Oshiyama, Y Wada, H Shikano… - … on Languages and …, 2005 - Springer
With the increase of transistors integrated onto a chip, multi core processor architectures
have attracted much attention to achieve high effective performance, shorten development …

A packet switching communication-based test access mechanism for system chips

M Nahvi, A Ivanov - European Test Workshop, IEEE, 2001 - computer.org
This paper describes multigrain parallel processing on a compiler cooperative chip
multiprocessor. The multigrain parallel processing hierarchically exploits multiple grains of …

Performance evaluation of oscar multi-target automatic parallelizing compiler on intel, amd, arm and risc-v multicores

BM Magnussen, T Kawasumi, H Mikami… - … on Languages and …, 2021 - Springer
With an increasing number of shared memory multicore processor architectures, there is a
requirement for supporting multiple architectures in automatic parallelizing compilers. The …

A parallelizing compiler cooperative heterogeneous multicore processor architecture

Y Wada, A Hayashi, T Masuura, J Shirako… - Transactions on High …, 2011 - Springer
Heterogeneous multicore architectures, integrating several kinds of accelerator cores in
addition to general purpose processor cores, have been attracting much attention to realize …

Performance evaluation of compiler controlled power saving scheme

J Shirako, M Yoshida, N Oshiyama, Y Wada… - … , ISHPC 2005, Nara …, 2008 - Springer
Multicore processors, or chip multiprocessors, which allow us to realize low power
consumption, high effective performance, good cost performance and short …

Reducing parallelizing compilation time by removing redundant analysis

J Han, R Fujino, R Tamura, M Shimaoka… - Proceedings of the 3rd …, 2016 - dl.acm.org
Parallelizing compilers equipped with powerful compiler optimizations are essential tools to
fully exploit performance from today's computer systems. These optimizations are supported …

Evaluation of power consumption at execution of multiple automatically parallelized and power controlled media applications on the rp2 low-power multicore

H Mikami, S Kitaki, M Mase, A Hayashi… - … and Compilers for …, 2013 - Springer
This paper evaluates an automatic power reduction scheme of OSCAR automatic
parallelizing compiler having power reduction control capability when multiple media …

Power-aware compiler controllable chip multiprocessor

H Shikano, J Shirako, Y Wada, K Kimura… - IEICE transactions on …, 2008 - search.ieice.org
A power-aware compiler controllable chip multiprocessor (CMP) is presented and its
performance and power consumption are evaluated with the optimally scheduled advanced …

[PDF][PDF] Hybrid analysis of memory references and its application to automatic parallelization.

SV Rus - 2006 - core.ac.uk
Executing sequential code in parallel on a multithreaded machine has been an elusive goal
of the academic and industrial research communities for many years. It has recently become …