A -Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier

J Ou, PM Ferreira - IEEE Transactions on Circuits and Systems …, 2014 - ieeexplore.ieee.org
Noise optimization is a challenging problem for nanoscale metal-oxide-silicon field-effect
transistor circuits. This brief presents a technique that uses transconductance-to-drain …

Design and analysis of folded cascode OTAs using Gm/Id methodology based on flicker noise reduction

M Akbari, O Hashemipour - Analog Integrated Circuits and Signal …, 2015 - Springer
In this paper, a new methodology for design of folded cascode (FC) and recycling folded
cascode (RFC) OTAs based on 1/f noise reduction is presented. With a new formulation for …

High accuracy potentiostat with wide dynamic range and linearity

S Toprak, RA Vural, OZ Batur - AEU-International Journal of Electronics …, 2021 - Elsevier
Electrochemical measurement require potentiostat to ensure the operational stability during
the sensing and conversion of the sensor signals. This article presents a potentiostat circuit …

Design technique for regulated cascode transimpedance amplifier using Gm/ID methodology

MM Elbadry, MY Makkey, M Abdelgawad, M Atef - Microelectronics Journal, 2020 - Elsevier
This paper presents an approach using gm/ID methodology for the design of the regulated
cascode circuit (RGC) transimpedance amplifier (TIA) for optical receivers. The framework …

Design framework for inverter cascode transimpedance amplifier using Gm/ID based PSO applying design equations

MM Elbadry, MY Makkey, M Atef - AEU-International Journal of Electronics …, 2021 - Elsevier
This paper presents a framework for the design of the inverter cascode (InvCas)
transimpedance (TIA) for the optical receiver's front-end. The framework combines the …

Automated sizing of low-noise CMOS analog amplifier using ALCPSO optimization algorithm

CL Singh, C Anandini, AJ Gogoi… - Journal of Information …, 2018 - Taylor & Francis
The main aim of the automated design methodology is to improve the design process in
terms of cost, robustness and performance. Presence of noise restricts the minimum level of …

Analysis and optimization of noises of an analog circuit via PSO algorithms

CL Singh, KL Baishnab, C Anandini - Microsystem Technologies, 2019 - Springer
The strategy for analysis of noise generated in the analog circuit is presented here. Further,
methodology for optimization of noise to improve the performance of the circuit using an …

Closed-form and technology independent phase noise relation for LC oscillators

M Moradnezhad, H Miar-Naimi - COMPEL-The international journal …, 2023 - emerald.com
Purpose The purpose of this paper is to find a closed relation for the phase noise of LC
oscillators. Design/methodology/approach The governing equation of oscillators is generally …

An Efficient Design of 45nm Charge-Pump Phase-Locked Loop Architecture for Sub-1G IoT Applications

T Hoang, HT Nguyen, PTB Ton - IEEJ Transactions on Sensors and …, 2024 - jstage.jst.go.jp
Amid the rapid advancements in technology, the Internet of Things (IoT) has become a
pivotal element in the realm of wireless communication. The sub-1GHz network, in …

Low-noise CMOS differential-amplifier design using automated-design methodology

CL Singh, AJ Gogoi, C Anandini… - 2017 Devices for …, 2017 - ieeexplore.ieee.org
The increasing complexity of Integrated Circuits (ICs) and requirement of accurate design,
made the automated design technique a necessity. The design of analog circuit involves …