This paper presents the design of a 60-GHz low-noise amplifier (LNA) in a 28-nm low-power
(LP) bulk CMOS process. As the technology is optimized for digital LP applications, the …

In this paper, the design and analysis of CMOS multicascode configuration with noise
reduction topology are proposed. Two low power and miniature low-noise amplifiers (LNAs) …

In this paper, the design and analysis of CMOS low-noise amplifiers (LNAs) with a magnetic
coupled technique in different cascode topologies are proposed. To minimize the noise …

This paper presents a CMOS millimeter-wave (mm-wave) receiver designed to meet the
challenges in low-power, ultra-broadband, phased-array systems with a large number of …

This letter presents a 57-66 GHz low phase variation variable gain amplifier (VGA) in
standard RF 65 nm CMOS process with a chip area of 0.25 mm 2. The phase compensation …

A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first
complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio …

In this paper, a novel design technique of common-gate inductive feedback is presented for
millimeter-wave low-noise amplifiers (LNAs). For this technique, by adopting a gate inductor …

(57) ABSTRACT A low-noise amplifier (LNA) includes a first cascode gain stage coupled to
an input node for increasing an amplitude of an RF input signal. A first variable gain network …

This paper presents the design and measurement of an interpolation-based low noise and
variable gain cell (IBA-cell) in the 60-GHz band, using a 40-nm CMOS technology. The …

A compact E-band power amplifier (PA) with gain-boosting and efficiency enhancement
technique is proposed and implemented in a 65-nm CMOS process. The proposed gain …