Synthesis of embedded software from synchronous dataflow specifications

SS Bhattacharyya, PK Murthy, EA Lee - Journal of VLSI signal processing …, 1999 - Springer
The implementation of software for embedded digital signal processing (DSP) applications
is an extremely complex process. The complexity arises from escalating functionality in the …

A constraint-based god-object method for haptic display

CB Zilles, JK Salisbury - Proceedings 1995 ieee/rsj …, 1995 - ieeexplore.ieee.org
Haptic display is the process of applying forces to a human" observer" giving the sensation
of touching and interacting with real physical objects. Touch is unique among the senses …

Parameterized dataflow modeling for DSP systems

B Bhattacharya… - IEEE Transactions on …, 2001 - ieeexplore.ieee.org
Dataflow has proven to be an attractive computation model for programming digital signal
processing (DSP) applications. A restricted version of dataflow, termed synchronous …

Software synthesis and code generation for signal processing systems

SS Bhartacharyya, R Leupers… - IEEE Transactions on …, 2000 - ieeexplore.ieee.org
The role of software is becoming increasingly important in the implementation of digital
signal processing (DSP) applications. As this trend intensifies, and the complexity of …

OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems

SS Bhattacharyya, G Brebner, JW Janneck… - ACM SIGARCH …, 2009 - dl.acm.org
This paper presents the OpenDF framework and recalls that dataflow programming was
once invented to address the problem of parallel computing. We discuss the problems with …

Scheduling for embedded real-time systems

F Balarin, L Lavagno, P Murthy… - IEEE Design & Test …, 1998 - ieeexplore.ieee.org
Scheduling for embedded real-time systems Page 1 REAL-TIME EMBEDDED SYSTEMS are
of- ten characterized by the need for running several tasks on a limited set of processing units …

A hierarchical multiprocessor scheduling system for DSP applications

JL Pino, SS Bhattacharyya… - Conference record of the …, 1995 - ieeexplore.ieee.org
This paper discusses a hierarchical scheduling framework which reduces the complexity of
scheduling synchronous data flow (SDF) graphs onto multiple processors. The core of this …

Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks

R Govindarajan, GR Gao, P Desai - … of VLSI signal processing systems for …, 2002 - Springer
Large-grain synchronous dataflow graphs or multi-rate graphs have the distinct feature that
the nodes of the dataflow graph fire at different rates. Such multi-rate large-grain dataflow …

Executing synchronous dataflow graphs on a SPM-based multicore architecture

J Choi, H Oh, S Kim, S Ha - Proceedings of the 49th Annual Design …, 2012 - dl.acm.org
In this paper we are concerned about executing synchronous dataflow (SDF) applications
on a multicore architecture where a core has a limited size of scratchpad memory (SPM) …

Scheduling for optimum data memory compaction in block diagram oriented software synthesis

S Ritz, M Willems, H Meyr - 1995 International Conference on …, 1995 - ieeexplore.ieee.org
For the design of complex digital signal processing systems, block diagram oriented
synthesis of real time software for programmable target processors has become an …