FPGA implementation of high performance digital down converter for software defined radio

D Datta, P Mitra, HS Dutta - Microsystem Technologies, 2022 - Springer
Digital down converter (DDC) is one of the crucial components in digital radio receiver. The
working function of DDC is to convert the frequency translation from Intermediate Frequency …

Rate-distortion model for grayscale-invariance reversible data hiding

S Zhou, W Zhang, C Shen - Signal Processing, 2020 - Elsevier
Recently, a novel scheme called grayscale-invariance reversible data hiding (RDH) has
been developed, in which the generated color marked image will have the same grayscale …

A digital watermarking encryption technique based on FPGA cloud accelerator

Y Cao, F Yu, Y Tang - IEEE Access, 2020 - ieeexplore.ieee.org
Digital watermarking has the properties such as invisibility and anti-aggression, so the
digital watermarking technology has been widely used in copyright protection, information …

Efficient FPGA implementation of corrected reversible contrast mapping algorithm for video watermarking

S Das, AK Sunaniya, R Maity, NP Maity - Microprocessors and …, 2020 - Elsevier
This paper analyses and rectifies the shortcomings of reversible contrast mapping (RCM)
algorithm for invisible watermarking. The proposed corrected RCM algorithm is tested by …

FPGA implementation of lifting-based data hiding scheme for efficient quality access control of images

A Phadikar, GK Maity, TL Chiu, H Mandal - Circuits, Systems, and Signal …, 2019 - Springer
In this paper, a hardware implementation of a data hiding technique is proposed for efficient
quality access control of images using lifting-based discrete wavelet transformation (DWT) …

Efficient FPGA implementation of chaos-based real-time video watermarking system in spatial and DWT domain using QIM technique

NE Aissaoui, MS Azzaz, R Kaibou… - Journal of Real-Time …, 2025 - Springer
This paper introduces an efficient, lightweight, invisible, blind, real-time video watermarking
system. Symmetric chaotic key encryption enhances the system's security, ensuring …

Efficient FPGA implementation and verification of difference expansion based reversible watermarking with improved time and resource utilization

S Das, AK Sunaniya, R Maity, NP Maity - Microprocessors and …, 2021 - Elsevier
Abstract This paper presents Xilinx System Generator (XSG) model design for realization of
reversible watermarking algorithm using Difference Expansion (DE) approach in System-On …

FPGA implementation of high-fidelity hybrid reversible watermarking algorithm

S Das, AK Sunaniya - Microprocessors and Microsystems, 2022 - Elsevier
In the digitally dominated world, to enhance the data security of digital images, this paper
proposes a hybrid algorithm. The algorithm enhances quality metrics and simultaneously …

Parallel hardware implementation of efficient embedding bit rate control based contrast mapping algorithm for reversible invisible watermarking

S Das, AK Sunaniya, R Maity, NP Maity - IEEE Access, 2020 - ieeexplore.ieee.org
This paper presents an improved reversible contrast mapping (RCM) algorithm for reversible
invisible watermarking (RIW) in both software and hardware platforms. Based on well-known …

Area-efficient low-power image watermarking architecture using faithful approximation and reversible logic

V KN, SK - Multimedia Tools and Applications, 2024 - Springer
Approximate computing and reversible logic have become vital concepts in designing low-
power, area-efficient datapath units for portable image and signal processing applications …