By viewing noise as a resource rather than as an impediment, we demonstrate an entirely
novel approach to ultra low-energy computing. The subject of this study is the probabilistic …

In this paper, we investigate the impact of interconnect and device process variations on
voltage fluctuations in power grids. We consider random variations in the power grid's …

Power supply noise is becoming more and more influential on timing, though noise aware
timing analysis has not been well established yet, because of several difficulties such as its …

As part of the design of large integrated circuits, one must verify that the power delivery
network provides supply and ground voltages to the circuit that are within specified ranges …

This paper solves the variation-aware decoupling capacitance (decap) budgeting problem.
Unlike previous works which only consider worst case design, for the first time, we consider …

This paper proposes a novel stochastic method for analyzing the voltage drop variations of
on-chip power grid networks, considering lognormal leakage current variations. The new …

Since process variation and chip performance uncertainties have become more pronounced
as technologies scale down into the nanometer regime, accurate and efficient modeling or …

On-chip true random number generators (TRNGs) can be designed by using traditional
CMOS technology or by using more recent nanoscale devices and technologies. In CMOS …

As part of early system design, one must verify that the power grid provides the underlying
logic circuitry with voltage levels that are within specified ranges. In this paper, we describe …

VLSI timing analysis and power estimation target the same circuit switching activity. Power
estimation techniques are categorized as (1) static,(2) statistical, and (3) simulation and …