Methods for fault tolerance in networks-on-chip
Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …
components increases, network-on-chip (NoC) architectures have been recently proposed …
Addressing transient and permanent faults in NoC with efficient fault-tolerant deflection router
Continuing decrease in the feature size of integrated circuits leads to increases in
susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution …
susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution …
The chip is the network: Toward a science of network-on-chip design
R Marculescu, P Bogdan - Foundations and Trends® in …, 2009 - nowpublishers.com
In this survey, we address the concept of network in three different contexts representing the
deterministic, probabilistic, and statistical physics-inspired design paradigms. More …
deterministic, probabilistic, and statistical physics-inspired design paradigms. More …
On hamming product codes with type-II hybrid ARQ for on-chip interconnects
B Fu, P Ampadu - IEEE Transactions on Circuits and Systems I …, 2009 - ieeexplore.ieee.org
We present hardware performance analyses of Hamming product codes combined with type-
II hybrid automatic repeat request (HARQ), for on-chip interconnects. Input flit width and the …
II hybrid automatic repeat request (HARQ), for on-chip interconnects. Input flit width and the …
Self-adaptive system for addressing permanent errors in on-chip interconnects
We present a self-contained adaptive system for detecting and bypassing permanent errors
in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of …
in on-chip interconnects. The proposed system reroutes data on erroneous links to a set of …
A case study in reliability-aware design: A resilient LDPC code decoder
M May, M Alles, N Wehn - Proceedings of the conference on Design …, 2008 - dl.acm.org
Chip reliability becomes a great threat to the design of future microelectronic systems with
the continuation of the progressive downscaling of CMOS technologies. Hence increasing …
the continuation of the progressive downscaling of CMOS technologies. Hence increasing …
Dependable multicore architectures at nanoscale: The view from europe
This article presented a survey of dependability issues faced by multi-core architectures at
nanoscale technology nodes. Existing solutions against these challenges were also …
nanoscale technology nodes. Existing solutions against these challenges were also …
NH vs. CH hydrogen bond formation in metal–organic anion receptors containing pyrrolylpyridine ligands
NH vs. CH hydrogen bond formation in metal–organic anion receptors containing
pyrrolylpyridine ligands - Chemical Communications (RSC Publishing) DOI:10.1039/B510506D …
pyrrolylpyridine ligands - Chemical Communications (RSC Publishing) DOI:10.1039/B510506D …
Reliable low power NoC interconnect
M Vinodhini, NS Murty - Microprocessors and Microsystems, 2018 - Elsevier
Abstract Information communicated through Network on Chip (NoC) in System on Chip
(SoC) is highly prone to different sources of noise, like coupling, radiation and …
(SoC) is highly prone to different sources of noise, like coupling, radiation and …