In this paper we present a novel processor microarchitecture that relieves, four of the most
important bottlenecks of superscalar processors: the serialization imposed by true …

Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be
possible using the techniques described herein. Traditional speculative code execution is …

Superscalar processors currently have the potential to fetch multiple basic blocks per cycle
by employing one of several recently proposed instruction fetch mechanisms. However, this …

Traditional vector architectures have shown to be very effective for regular codes where the
compiler can detect data-level parallelism. However, this SIMD parallelism is also present in …

Several ILP limit studies indicate the presence of considerable ILP across dynamically far-
apart instructions in program execution. This paper proposes a hardware mechanism …

In this paper we present a run-time mechanism to simultaneously execute multiple threads
from a sequential program on a simultaneous multithreaded (SMT) processor. The threads …

A reduced set of procedural dependencies is presented which is necessary and sufficient to
describe all procedural dependencies in standard imperative codes. Hence, the set is …

This thesis examines nonloop parallelism at both fine and coarse levels of granularity in
numerical FORTRAN programs. Measurements of the extent of this functional parallelism in …

The Levo high IPC microarchitecture is described and evaluated. Levo employs instruction
time-tags and Active Stations to ensure correct operation in a rampantly speculative and out …

Our goal is to dramatically increase the performance of uniprocessors through the
exploitation of instruction level parallelism, ie that parallelism which exists amongst the …