A low-power comparator is presented. pMOS transistors are used at the input of the
preamplifier of the comparator as well as the latch stage. Both stages are controlled by a …

An ultra-low voltage, ultra-low power rail-to-rail dynamic voltage comparator solely based on
digital standard cells is presented. Thanks to its digital nature, the comparator can be …

A novel rail-to-rail dynamic voltage comparator is presented in this paper. The proposed
circuit is fully synthesizable, as it can be designed with automated digital design flows and …

A high-resolution dynamic voltage comparator with an input signal dependent power down
technique for low power applications is presented here. Without affecting the resolution, a …

Training deep learning networks involves continuous weight updates across the various
layers of the deep network while using a backpropagation (BP) algorithm. This results in …

A low‐power technique for high‐resolution comparators is introduced. In this technique, p‐
type metal‐oxide‐semiconductor field‐effect transistors are employed as the input of the …

Brain-inspired Hyperdimensional Computing (HDC) is a fast and robust classification
algorithm, which works by mapping low-dimensional features to high-dimensional vectors …

This paper presents a 12-bit 10 MS/s successive approximation register analog-to-digital
converter (SAR ADC) based on the extended C–2C capacitor array. Compared with …

Reduced voltage head room availability for input signal swing is one of the major
bottlenecks in the design of circuits operating with low supply voltages which attracts …

A charge sharing technique for high-speed double-tail comparators is presented. This
technique is applied to the pre-amplifier stage of the dynamic comparators so that the …