Analog-to-digital converters (ADCs) are critical components of signal-processing systems.
ADC errors can compromise the overall accuracy and the effectiveness of the whole system …

The proposed digital background calibration scheme, applicable to multistage (pipelined or
algorithmic/cyclic) analog-to-digital converters (ADCs), corrects the linearity errors resulting …

We present an adaptive digital technique to calibrate pipelined analog-to-digital converters
(ADCs). Rather than achieving linearity by adjustment of analog component values, the new …

A low-power 10-bit converter that can sample input frequencies above 100 MHz is
presented. The converter consumes 55 mW when sampling at f/sub s/= 40 MHz from a 3-V …

A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor
mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels …

This paper presents a prototype analog-to-digital converter (ADC) that uses a calibration
algorithm to adaptively overcome constant closed-loop gain errors, closed-loop gain …

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the
background using an algorithmic ADC, which is itself calibrated in the foreground. The …

For four decades the evolution of integrated circuits has followed Moore's law, according to
which the number of transistors per square millimeter of silicon doubles every 18 months. At …

The design of a multibit/spl Delta//spl Sigma/converter is presented. It uses a third-order 4-
bit/spl Delta//spl Sigma/topology with data weighted averaging (DWA) to reduce the linearity …

An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate
a 12-b algorithmic analog-to-digital converter in the background. At a sampling rate of 125 …