A survey of software techniques for using non-volatile memories for storage and main memory systems

S Mittal, JS Vetter - IEEE Transactions on Parallel and …, 2015 - ieeexplore.ieee.org
Non-volatile memory (NVM) devices, such as Flash, phase change RAM, spin transfer
torque RAM, and resistive RAM, offer several advantages and challenges when compared …

A survey of techniques for modeling and improving reliability of computing systems

S Mittal, JS Vetter - IEEE Transactions on Parallel and …, 2015 - ieeexplore.ieee.org
Recent trends of aggressive technology scaling have greatly exacerbated the occurrences
and impact of faults in computing systems. This has madereliability'a first-order design …

A large-scale empirical study on self-admitted technical debt

G Bavota, B Russo - Proceedings of the 13th international conference …, 2016 - dl.acm.org
Technical debt is a metaphor introduced by Cunningham to indicate" not quite right code
which we postpone making it right". Examples of technical debt are code smells and bug …

Delegated persist ordering

A Kolli, J Rosen, S Diestelhorst, A Saidi… - 2016 49th Annual …, 2016 - ieeexplore.ieee.org
Systems featuring a load-store interface to persistent memory (PM) are expected soon,
making in-memory persistent data structures feasible. Ensuring persistent data structure …

NVM Duet: Unified working memory and persistent store architecture

RS Liu, DY Shen, CL Yang, SC Yu… - ACM SIGARCH Computer …, 2014 - dl.acm.org
Emerging non-volatile memory (NVM) technologies have gained a lot of attention recently.
The byte-addressability and high density of NVM enable computer architects to build large …

Compex++ compression-expansion coding for energy, latency, and lifetime improvements in mlc/tlc nvms

PM Palangappa, K Mohanram - ACM Transactions on Architecture and …, 2017 - dl.acm.org
Multilevel/triple-level cell nonvolatile memories (MLC/TLC NVMs) such as phase-change
memory (PCM) and resistive RAM (RRAM) are the subject of active research and …

Tri-level-cell phase change memory: Toward an efficient and reliable memory system

NH Seong, S Yeo, HHS Lee - Proceedings of the 40th Annual …, 2013 - dl.acm.org
There are several emerging memory technologies looming on the horizon to compensate
the physical scaling challenges of DRAM. Phase change memory (PCM) is one such …

HARP: Practically and effectively identifying uncorrectable errors in memory chips that use on-die error-correcting codes

M Patel, GF de Oliveira, O Mutlu - MICRO-54: 54th Annual IEEE/ACM …, 2021 - dl.acm.org
Aggressive storage density scaling in modern main memories causes increasing error rates
that are addressed using error-mitigation techniques. State-of-the-art techniques for …

Mitigating write disturbance in super-dense phase change memories

L Jiang, Y Zhang, J Yang - 2014 44th Annual IEEE/IFIP …, 2014 - ieeexplore.ieee.org
Constructing a highly scalable and dense main memory subsystem with large access
bandwidth has become a major challenge for modern computing systems. Traditional …

A case for self-managing DRAM chips: Improving performance, efficiency, reliability, and security via autonomous in-DRAM maintenance operations

H Hassan, A Olgun, AG Yaglikci, H Luo, O Mutlu - arXiv, 2022 - research-collection.ethz.ch
The memory controller is in charge of managing DRAM maintenance operations (eg,
refresh, RowHammer protection, memory scrubbing) in current DRAM chips. Implementing …