Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

R Marculescu, UY Ogras, LS Peh… - … on computer-aided …, 2008 - ieeexplore.ieee.org
To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

Key research problems in NoC design: a holistic perspective

UY Ogras, J Hu, R Marculescu - Proceedings of the 3rd IEEE/ACM/IFIP …, 2005 - dl.acm.org
Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex
on-chip communication problems. The lack of an unified representation of applications and …

Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees

S Murali, L Benini, G De Micheli - Proceedings of the 2005 Asia and …, 2005 - dl.acm.org
Networks on Chips (NoCs) have evolved as the communication design paradigm of future
Systems on Chips (SoCs). In this work we target the NoC design of complex SoCs with …

The chip is the network: Toward a science of network-on-chip design

R Marculescu, P Bogdan - Foundations and Trends® in …, 2009 - nowpublishers.com
In this survey, we address the concept of network in three different contexts representing the
deterministic, probabilistic, and statistical physics-inspired design paradigms. More …

A design methodology for application-specific networks-on-chip

J Xu, W Wolf, J Henkel, S Chakradhar - ACM Transactions on Embedded …, 2006 - dl.acm.org
With the help of HW/SW codesign, system-on-chip (SoC) can effectively reduce cost,
improve reliability, and produce versatile products. The growing complexity of SoC designs …

[图书][B] Heterogeneous computing: Hardware and software perspectives

M Zahran - 2019 - books.google.com
If you look around you will find that all computer systems, from your portable devices to the
strongest supercomputers, are heterogeneous in nature. The most obvious heterogeneity is …

A mesh-of-trees interconnection network for single-chip parallel processing

AO Balkan, G Qu, U Vishkin - IEEE 17th International …, 2006 - ieeexplore.ieee.org
There is a recent surge of interest in single-chip parallel processors. In such machines, it is
crucial to implement a high-throughput low-latency interconnection network to connect the …

Floorplan optimization of fat-tree-based networks-on-chip for chip multiprocessors

Z Wang, J Xu, X Wu, Y Ye, W Zhang… - IEEE Transactions …, 2012 - ieeexplore.ieee.org
Chip multiprocessor (CMP) is becoming increasingly popular in the processor industry.
Efficient network-on-chip (NoC) that has similar performance to the processor cores is …

CNoC: high-radix clos network-on-chip

YH Kao, M Yang, NS Artan… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
Many high-radix network-on-chip (NoC) topologies have been proposed to improve network
performance with an ever-growing number of processing elements (PEs) on a chip. We …

Mesh-of-trees and alternative interconnection networks for single-chip parallelism

AO Balkan, G Qu, U Vishkin - IEEE Transactions on Very Large …, 2009 - ieeexplore.ieee.org
In single-chip parallel processors, it is crucial to implement a high-throughput low-latency
interconnection network to connect the on-chip components, especially the processing units …