Soft errors in combinational logic circuits are emerging as a significant reliability concern for
nanoscale VLSI designs. This paper presents a novel sensitivity-based gate sizing …

В настоящее время актуальность исследований в области повышения надежности
функционирования микроэлектронных систем неуклонно возрастает. Во многом это …

Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making
the soft error rate (SER) estimation an important challenge. In this study, a novel approach is …

Increasing the operating reliability of integrated microcircuits (IMC) remains, on the whole,
an unsolved design problem. An important aspect of this problem is the stability of the …

As the technology scaling enters into the nanoscale regime, soft errors become one of the
major challenging issues for VLSI chips. Susceptibility to soft error is even becoming more …

Aging and soft errors have become the two most critical reliability issues for nano-scaled
CMOS designs. In this paper, the aging effect due to negative bias temperature instability …

В данной статье рассматривается проблема повышения сбоеустойчивости
применительно к комбинационным ИМС. Под сбоем комбинационной схемы …

В настоящее время в связи с необходимостью обеспечения повышенных
характеристик радиационной стойкости и сбоеустойчивости комбинационных схем …

Soft error rate (SER) has become a critical reliability issue for CMOS designs due to
continuous technology scaling. However, the striking-time and multi-cycle effects have not …

Experimental results from a 65 nm CMOS commercial technology SRAM test chip reveal a
linear correlation between a new electrical parameter-the word-line voltage margin (V …