Field programmable gate array applications—A scientometric review

J Ruiz-Rosero, G Ramirez-Gonzalez, R Khanna - Computation, 2019 - mdpi.com
Field Programmable Gate Array (FPGA) is a general purpose programmable logic device
that can be configured by a customer after manufacturing to perform from a simple logic gate …

[PDF][PDF] Implementation of multiplier using Vedic algorithm

M Poornima, SK Patil, SKP Shivukumar… - International journal of …, 2013 - Citeseer
Vedic mathematics is the name given to the ancient Indian system of mathematics that was
rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). This …

Design and evaluation of cell interaction based vedic multiplier using quantum-dot cellular automata

N Safoev, JC Jeon - Electronics, 2020 - mdpi.com
A multiplier is one of the main units for digital signal processing and communication
systems. In this paper, a high speed and low complexity multiplier is designed on the basis …

[PDF][PDF] High Speed Efficient N x N Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematics

H Thapliyal, MB Srinivas - Enformatika Trans, 2004 - Citeseer
A NXN bit parallel overlay multiplier architecture is designed for high speed DSP operations.
The architecture is based on the vertical and crosswise algorithm of ancient Indian Vedic …

High speed vedic multiplier for digital signal processors

R Pushpangadan, V Sukumaran, R Innocent… - IETE journal of …, 2009 - Taylor & Francis
Digital signal processors (DSPs) are very important in various engineering disciplines. Fast
multiplication is very important in DSPs for convolution, Fourier transforms etc. A fast method …

[PDF][PDF] Implementation of an efficient multiplier based on vedic mathematics using eda tool

P Verma, KK Mehta - International Journal of Engineering and …, 2012 - kresttechnology.com
A high speed processor depends greatly on the multiplier as it is one of the key hardware
blocks in most digital signal processing systems as well as in general processors. This …

An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata

A Chudasama, TN Sasamal, J Yadav - Computers & Electrical Engineering, 2018 - Elsevier
Abstract Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies,
which yields attractive features like high speed, low power consumption and smaller size for …

Design and implementation of efficient multiplier using Vedic mathematics

JM Rudagi, V Ambli, V Munavalli… - … on advances in …, 2011 - ieeexplore.ieee.org
Multiplication is an important fundamental function in arithmetic operations. Multiplication-
based operations such as Multiply and Accumulate (MAC) and inner product are among …

[PDF][PDF] Design of 4x4 bit vedic multiplier using EDA tool

P Verma - International Journal of Computer Applications, 2012 - Citeseer
The need of high speed multiplier is increasing as the need of high speed processors are
increasing. A Multiplier is one of the key hardware blocks in most fast processing system …

Design and implementation of two variable multiplier using KCM and vedic mathematics

L Sriraman, TN Prabakar - 2012 1st international conference on …, 2012 - ieeexplore.ieee.org
In this paper, a novel multiplier architecture based on ROM approach using Vedic
Mathematics is proposed. This multiplier's architecture is similar to that of a Constant Co …