A comprehensive review on the VLSI design performance of different Parallel Prefix Adders
Adders are an important part of digital systems. In VLSI digital circuits, such adders should
satisfy certain design constraints like low power and high speed. In this paper we present a …
satisfy certain design constraints like low power and high speed. In this paper we present a …
[PDF][PDF] Implementation of body movement detection system for coma patients using WSN
M Dhamodaran, T Praveen, GS Rishaban… - … Journal of Grid and …, 2020 - researchgate.net
Movement detection due to physical changes is a very important tool and it is important to
monitor the unconscious/coma patients in order to gain details about the health condition …
monitor the unconscious/coma patients in order to gain details about the health condition …
An area efficient network on chip architecture using high performance pipelines FIFO technique
S Sariga, C Nandagopal - 2017 IEEE International Conference …, 2017 - ieeexplore.ieee.org
Most correspondence movement in today's Network on Chips (NOC) depends on switch for
unstable memory based outlines. The NOC ought to be intended to effectively deal with the …
unstable memory based outlines. The NOC ought to be intended to effectively deal with the …
[PDF][PDF] Variable Latency Approach in VLSI Adder Implemented to Reduce Area and Power
K Kaarthik, C Vivek - Indian Journal …, 2018 - sciresol.s3.us-east-2.amazonaws …
Abstract Objective: The Ultimate aim of the VLSI Design is to improve the efficiency,
Reduction of Delay and Power Consumption and to minimize the area. In our proposed …
Reduction of Delay and Power Consumption and to minimize the area. In our proposed …
Design and Performance Analysis of Full Adder Circuit Using Different Logic Styles
A significant development has been seen in the field of Integrated circuits (IC) technology.
With the fast-growing world, we want our ICs to be fast, should occupy less area by less …
With the fast-growing world, we want our ICs to be fast, should occupy less area by less …
Optimization of the acyclic adders of binary codes
M Solomko - Технологический аудит и резервы производства, 2018 - cyberleninka.ru
The object of research is a prefix model for calculating adding and transport signals in a
parallel adder circuit with a parallel transfer method. One of the most problematic places in …
parallel adder circuit with a parallel transfer method. One of the most problematic places in …
[PDF][PDF] Automatic Ration Material Distributions Based on GSM and RFID Technology
G MURUGANANTHAM, A ELAVARASI - chettinadtech.ac.in
Nowadays ration card is exceptionally basic for every single house and it is utilized as a part
of different fields, for example, relative's points of interest, to get gas association, Domicile …
of different fields, for example, relative's points of interest, to get gas association, Domicile …
Tuberculosis malady recognition in chest radiographs via artificial neural networks
A Sridevi, GKDP Venkatesan - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
This proposed method will give a suggestion for Tuberculosis (TB) diagnosing using
Artificial Neural Networks (ANN). Since diagnostic imaging techniques such as x-rays …
Artificial Neural Networks (ANN). Since diagnostic imaging techniques such as x-rays …
[PDF][PDF] Только для чтения
ОАСБ КОДІВ - journals.uran.ua
DOI: 10.15587/2312-8372.2018.133694 ОПТИМІЗАЦІЯ АЦИКЛІЧНИХ СУМАТОРІВ БІНАРНИХ
КОДІВ Page 1 DOI: 10.15587/2312-8372.2018.133694 ОПТИМІЗАЦІЯ АЦИКЛІЧНИХ …
КОДІВ Page 1 DOI: 10.15587/2312-8372.2018.133694 ОПТИМІЗАЦІЯ АЦИКЛІЧНИХ …
[PDF][PDF] ОптимізаціЯ ациклічниХ суматоріВ бінарниХ кодіВ
M Solomko - Technology Audit and Production Reserves - journals.uran.ua
Завдяки цьому забезпечується можливість отримання оптимальних значень показників
складності структури та глибини схеми суматора. Зв'язок між числом обчислювальних …
складності структури та глибини схеми суматора. Зв'язок між числом обчислювальних …