An arithmetic circuit includes an input buffer latching each of a plurality of input signals,
sequentially input, and sequentially outputting a plurality of first addition signals and a …

US20230041850A1 - Adaptive matrix multiplication accelerator for machine learning and
deep learning applications - Google Patents US20230041850A1 - Adaptive matrix …

Discussed herein are devices, systems, and methods for efficient sparse matrix factorization.
A method can include writing matrix data representing a sparse matrix to a memory, after …

An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first
multiplying unit a second multiplying unit, a memory load circuit, and an outer buffer circuit …