The HERA methodology: reconfigurable logic in general-purpose computing

P Holzinger, M Reichenbach - IEEE Access, 2021 - ieeexplore.ieee.org
Due to the ongoing slowdown of Dennard scaling, heterogeneous hardware architectures
are inevitable to meet the increasing demand for energy efficient systems. However, one of …

Malicious attack prevention through cartography of co-processors at datacenter

KS Fine, E Kruglick - US Patent 9,237,165, 2016 - Google Patents
The present disclosure generally describes techniques for malicious attack prevention
through cartography of co-pro-35 cessors at a datacenter. According to Some examples, a …

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures

D Stroobandt, AL Varbanescu… - … -centric Systems-on …, 2016 - ieeexplore.ieee.org
To handle the stringent performance requirements of future exascale-class applications,
High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute …

1+ 1< 2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area Saving

L Feng, J Sha, Z Wang - IEEE Transactions on Computer-Aided …, 2023 - ieeexplore.ieee.org
In the field of digital VLSI design, multimode circuits are the designs where the modes can
be switched according to different application scenarios, and are commonly used in …

Ant colony optimization for multicore re-configurable architecture

I Hussain, A Ahmad, MY Qadri, NN Qadri… - AI …, 2016 - content.iospress.com
Abstract The emergence of Multi Processor System on Chip (MPSoC) architectures with
reconfigurable options is revolutionizing general purpose processing. Reconfigurable …

Task scheduling on FPGA-based accelerators with limited partial reconfiguration

P Jungblut - 2024 - edoc.ub.uni-muenchen.de
Abstract Field Programmable Gate Arrays (FPGAs) are integrated circuits that can be
reconfigured dynamically. Accelerators for offloading computation based on FPGAs …

RTRLib: A High-Level Modeling Tool for the Implementation of Dynamically Partial Reconfigurable System-on-Chips

RM Ivo, DM Muñoz - 2019 International Conference on …, 2019 - ieeexplore.ieee.org
Partial Reconfiguration allows the time-multiplexing resources to be explored,
accomplishing requirements such as adaptability, robustness, power consumption, cost, and …

An open reconfigurable research platform as stepping stone to exascale high-performance computing

D Stroobandt, CB Ciobanu… - … , Automation & Test …, 2017 - ieeexplore.ieee.org
To handle the stringent performance and power requirements of future exascale-class
applications, High Performance Computing (HPC) systems need ultra-efficient …

Automatic fpga-based hardware accelerator design: A case study with image processing applications

C Pham-Quoc - EAI Endorsed Transactions on Context-aware Systems …, 2020 - eudl.eu
We present a case study of automatic FPGA-based hardware accelerator design using our
proposed framework with the image processing domain. With the framework, the ultimate …

River: Reconfigurable flow and fabric for real-time signal processing on FPGAS

C Brugger, D Hillenbrand, M Balzer - ACM Transactions on …, 2014 - dl.acm.org
For high-performance embedded hard-real-time systems, ASICs and FPGAs hold
advantages over general-purpose processors and graphics accelerators (GPUs). However …