Spintronic devices: a promising alternative to CMOS devices

P Barla, VK Joshi, S Bhat - Journal of Computational Electronics, 2021 - Springer
The field of spintronics has attracted tremendous attention recently owing to its ability to offer
a solution for the present-day problem of increased power dissipation in electronic circuits …

Magnetic racetrack memory: From physics to the cusp of applications within a decade

R Bläsing, AA Khan, PC Filippou, C Garg… - Proceedings of the …, 2020 - ieeexplore.ieee.org
Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the
potential to overcome fundamental constraints of existing memory and storage devices. It is …

Shiftsreduce: Minimizing shifts in racetrack memory 4.0

AA Khan, F Hameed, R Bläsing, SSP Parkin… - ACM Transactions on …, 2019 - dl.acm.org
Racetrack memories (RMs) have significantly evolved since their conception in 2008,
making them a serious contender in the field of emerging memory technologies. Despite key …

Regless: Just-in-time operand staging for GPUs

J Kloosterman, J Beaumont, DA Jamshidi… - Proceedings of the 50th …, 2017 - dl.acm.org
The register file is one of the largest and most power-hungry structures in a Graphics
Processing Unit (GPU), because massive multithreading requires all the register state for …

Polyhedral compilation for racetrack memories

AA Khan, H Mewes, T Grosser… - … on Computer-Aided …, 2020 - ieeexplore.ieee.org
Traditional memory hierarchy designs, primarily based on SRAM and DRAM, become
increasingly unsuitable to meet the performance, energy, bandwidth, and area requirements …

Brain-inspired Cognition in Next-generation Racetrack Memories

AA Khan, S Ollivier, S Longofono, G Hempel… - ACM Transactions on …, 2022 - dl.acm.org
Hyperdimensional computing (HDC) is an emerging computational framework inspired by
the brain that operates on vectors with thousands of dimensions to emulate cognition. Unlike …

An energy-efficient GPGPU register file architecture using racetrack memory

M Mao, W Wen, Y Zhang, Y Chen… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Extreme multi-threading and fast thread switching in modern GPGPU require a large, power-
hungry register file (RF), which quickly becomes one of major obstacles on the upscaling …

Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads

AA Khan, NA Rink, F Hameed, J Castrillon - Proceedings of the 20th …, 2019 - dl.acm.org
Tensor contraction is a fundamental operation in many algorithms with a plethora of
applications ranging from quantum chemistry over fluid dynamics and image processing to …

Process variation aware data management for magnetic skyrmions racetrack memory

F Chen, Z Li, W Kang, W Zhao, H Li… - 2018 23rd Asia and …, 2018 - ieeexplore.ieee.org
Skyrmions racetrack memory (SKM) has been identified as a promising candidate for future
on-chip cache. Similar to many other nanoscale technologies, process variations also …

Smartphone processor architecture, operations, and functions: current state-of-the-art and future outlook: energy performance trade-off: Energy–performance trade-off …

Ginny, C Kumar, K Naik - The Journal of Supercomputing, 2021 - Springer
Balancing energy–performance trade-offs for smartphone processor operations is
undergoing intense research considering the challenges with the evolving technology of …