A nonplanar semiconductor device and its method of fabrication is described. The nonplanar
semiconductor device includes a semiconductor body having a top surface opposite a …

[0003] 2. Discussion of RelatedArt [0004] Multi-gate transistors have been under
development to address the short channel effect (SCE) a? licting planar nano-scale …

A contact architecture for nanoscale channel devices having contact structures coupling to
and extending between source or drain regions of a device having a plurality of parallel …

US8193567B2 - Process for integrating planar and non-planar CMOS transistors on a bulk
substrate and article made thereby - Google Patents US8193567B2 - Process for integrating …

The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a
module substrate, a thinned switch die residing over the module substrate, a first mold …

Described herein are a device utilizing a gate electrode mate rial with a single workfunction
for both the pMOS and nMOS transistors where the magnitude of the transistor threshold …

US7858481B2 - Method for fabricating transistor with thinned channel - Google Patents
US7858481B2 - Method for fabricating transistor with thinned channel - Google Patents …

(57) ABSTRACT A semiconductor device comprising a gate electrode formed on a gate
dielectric layer formed on a semiconductor film. A pair of Source/drain regions are formed …

A method of a bulk tri-gate transistor having stained enhanced mobility and its method of
fabrication. The present invention is a nonplanar transistor having a strained enhanced …

Described herein are a device utilizing a gate electrode mate rial with a single workfunction
for both the pMOS and nMOS transistors where the magnitude of the transistor threshold …