Diverse and wide-range applications of integrated circuits (ICs) and the development of
Cyber Physical System (CPS), more and more third-party manufacturers are involved in the …

As the ubiquity and complexity of system-on-chip (SoC) designs increase across electronic
devices, incorporating security into an SoC design flow poses significant challenges …

This article presents RTL-ConTest, a register transfer-level (RTL) security vulnerability
detection algorithm, that extracts critical process flows from a RTL design and executes RTL …

Modern System-on-Chip (SoC) designs include a variety of Network-on-Chip (NoC) fabrics
to implement coordination and communication of integrated hardware intellectual property …

Hardware IPs are assumed to be roots-of-trust in complex SoCs. However, their design and
security verification are still heavily dependent on manual expertise. Extensive research in …

Symbolic execution is a powerful verification tool for hardware designs, but suffers from the
path explosion problem. We introduce a new approach, piecewise composition, which …

Abstract Model checking is an effective technique for formal verification of hardware security
properties in order to detect security vulnerabilities. However, a major challenge lies in state …

We present SEIF, a methodology that combines static analysis with symbolic execution to
verify and explicate information flow paths in a hardware design. SEIF begins with a …

We present SEIF, an exploratory methodology for information flow verification based on
symbolic execution. SEIF begins with a statically built overapproximation of the information …

Symbolic execution is a powerful verification tool for hardware designs, in particular for
security validation. However, symbolic execution suffers from the path explosion problem in …