Double-gate junctionless 1T DRAM with physical barriers for retention improvement
MHR Ansari, N Navlakha, JY Lee… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
In this article, a double-gate (DG) junction-less (JL) transistor with physical barriers is
proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this …
proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this …
L-shaped tunnel field-effect transistor-based 1T DRAM with improved read current ratio, retention time, and sense margin
In this article, an L-shaped tunnel field-effect transistor (LTFET)-based one-transistor
dynamic random access memory (1T DRAM) with SiGe storage region was demonstrated …
dynamic random access memory (1T DRAM) with SiGe storage region was demonstrated …
Simulation study of multi-source hetero-junction tfet-based capacitor less 1t dram for low power applications
A capacitorless one-transistor dynamic random access memory (1T DRAM) based on multi-
source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The …
source hetero-junction tunnel field-effect transistor (TFET) is presented in this work. The …
Realizing logic functions using single double-gate tunnel FETs: A simulation study
In this letter, a single double-gate tunnel field-effect transistor (DGTFET) is proposed to
realize different logic functions and investigated using two-dimensional device simulations. It …
realize different logic functions and investigated using two-dimensional device simulations. It …
Retention and scalability perspective of sub-100-nm double gate tunnel FET DRAM
N Navlakha, JT Lin, A Kranti - IEEE Transactions on Electron …, 2017 - ieeexplore.ieee.org
This paper reports on the design optimization of double gate (DG) tunnel FET (TFET) for
dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral …
dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral …
Low-power and high-density neuron device for simultaneous processing of excitatory and inhibitory signals in neuromorphic systems
A positive-feedback (PF) neuron device capable of threshold tuning and simultaneously
processing excitatory () and inhibitory () signals is experimentally demonstrated to replace …
processing excitatory () and inhibitory () signals is experimentally demonstrated to replace …
Doping dependent assessment of accumulation mode and junctionless FET for 1T DRAM
MHR Ansari, N Navlakha, JT Lin… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper demonstrates the use of double-gate accumulation mode (AM) and junctionless
(JL) transistors for dynamic memory applications at 85° C. The doping dependent …
(JL) transistors for dynamic memory applications at 85° C. The doping dependent …
[HTML][HTML] Design of a capacitorless DRAM based on a polycrystalline-silicon dual-gate MOSFET with a fin-shaped structure
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell
based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor …
based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor …
1-T capacitorless DRAM using bandgap-engineered silicon-germanium bipolar I-MOS
In this paper, a 1-Transitor (1-T) capacitorless dynamic random access memory (DRAM)
using bandgap engineered silicon-germanium Bipolar ionization metal oxide semiconductor …
using bandgap engineered silicon-germanium Bipolar ionization metal oxide semiconductor …
1T-DRAM with shell-doped architecture
MHR Ansari, N Navlakha, JT Lin… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor
architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD …
architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD …