A survey of attacks on controller area networks and corresponding countermeasures

HJ Jo, W Choi - IEEE Transactions on Intelligent Transportation …, 2021 - ieeexplore.ieee.org
The development of vehicle technologies such as connected and autonomous vehicle
environments provide drivers with functions for convenience and safety that are highly …

Revisit sequential logic obfuscation: Attacks and defenses

T Meade, Z Zhao, S Zhang, D Pan… - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
The urgent requests to protection integrated circuits (IC) and hardware intellectual properties
(IP) have led to the development of various logic obfuscation methods. While most existing …

Scan-based side-channel attack against RSA cryptosystems using scan signatures

R Nara, K Satoh, M Yanagisawa, T Ohtsuki… - IEICE transactions on …, 2010 - search.ieice.org
Scan-based side-channel attacks retrieve a secret key in a cryptography circuit by analyzing
scanned data. Since they must be considerable threats to a cryptosystem LSI, we have to …

A bug you like: A framework for automated assignment of bugs

O Baysal, MW Godfrey, R Cohen - 2009 IEEE 17th …, 2009 - ieeexplore.ieee.org
Assigning bug reports to individual developers is typically a manual, time-consuming, and
tedious task. In this paper, we present a framework for automated assignment of bug-fixing …

New security threats against chips containing scan chain structures

J Da Rolt, G Di Natale, ML Flottes… - … on Hardware-Oriented …, 2011 - ieeexplore.ieee.org
Insertion of scan chains is the most common technique to ensure observability and
controllability of sequential elements in an IC. However, when the chip deals with secret …

Scan attacks and countermeasures in presence of scan response compactors

J DaRolt, G Di Natale, ML Flottes… - 2011 Sixteenth IEEE …, 2011 - ieeexplore.ieee.org
The conflict between security and testability is still a concern of hardware designers. While
secure devices must protect confidential information from unauthorized users, quality testing …

Dynamically changeable secure scan architecture against scan-based side channel attack

Y Atobe, Y Shi, M Yanagisawa… - 2012 International SoC …, 2012 - ieeexplore.ieee.org
Scan test which is one of the useful design for testability techniques is effective for LSIs
including cryptographic circuit. It can observe and control the internal states of the circuit …

Ensuring cryptography chips security by preventing scan-based side-channel attacks with improved DFT architecture

W Wang, X Wang, J Wang, NN Xiong… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Cryptography chips are often used in some applications, such as smart grids and Internet of
Things (IoT) to ensure their security. Cryptographic chips must be strictly tested to guarantee …

A brief review on jtag security

K Lee, Y Lee, H Lee, K Yim - 2016 10th International …, 2016 - ieeexplore.ieee.org
In this paper, we outline security issues on IEEE 1149.1 JTAG. The JTAG interface is
provided for its beneficial features, such as debugging and downloading firmware, but …

SSTKR: Secure and testable scan design through test key randomization

MA Razzaq, V Singh, A Singh - 2011 Asian Test Symposium, 2011 - ieeexplore.ieee.org
Scan test is the standard method, practiced by industry, that has consistently provided high
fault coverage due to high controllability and high observability. The scan chain allows to …