Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit

P Bhattacharyya, B Kundu, S Ghosh… - … Transactions on very …, 2014 - ieeexplore.ieee.org
In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–
semiconductor (CMOS) logic and transmission gate logic is reported. The design was first …

Design of a two-bit magnitude comparator based on pass transistor, transmission gate and conventional static CMOS logic

S Lubaba, KM Faisal, MS Islam… - 2020 11th International …, 2020 - ieeexplore.ieee.org
Since there is a swift technological progress going on in the recent years, semiconductor
industry evolved to such an extend that requirement of optimal performance in electronic …

[PDF][PDF] Comparative performance analysis of XORXNOR function based high-speed CMOS full adder circuits for low voltage VLSI design

S Wairya, RK Nagaria, S Tiwari - International Journal of VLSI …, 2012 - academia.edu
This paper presents comparative study of high-speed, low-power and low voltage full adder
circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A …

Full-adder circuit design based on all-spin logic device

Q An, L Su, JO Klein, S Le Beux… - Proceedings of the …, 2015 - ieeexplore.ieee.org
Limiting or reducing the power consumption of the digital circuits for calculation is now the
main concern in nanoelectronic domain. For this purpose, spintronic devices are proposed …

Performance evolution of 4-b bit MAC unit using hybrid GDI and transmission gate based adder and multiplier circuits in 180 and 90 nm technology

N Kandasamy, F Ahmad, S Reddy, N Telagam… - Microprocessors and …, 2018 - Elsevier
This paper presents the high-speed adder circuit design based on 18 transistor (18T) full
swing gate diffusion input based logic gates and transmission based techniques to compute …

Cell optimization and realization of MGDI and QCA based combinational logic circuits for nanotechnology applications

D Tripathi, S Sana, S Wairya - 2020 IEEE 17th India Council …, 2020 - ieeexplore.ieee.org
A modern computation paradigm towards nano-ICs, Quantum-dot Cellular Automata (QCA)
has picked up fame. QCA is appreciated due to its less power consumption, fast speed, and …

[PDF][PDF] Area and power efficient CMOS adder design by hybridizing PTL and GDI technique

A Sharma, R Mehra - International Journal of Computer Applications, 2013 - Citeseer
In this paper an area and power efficient 9T adder design has been presented by
hybridizing PTL and GDI techniques. The proposed adder design consist of 5 NMOS and 4 …

Low power 3-input AND/XOR gate design

H Liang, Y Xia, L Qian, C Huang - Journal of Computer-Aided Design & …, 2015 - jcad.cn
input AND/XOR gate is the basic complex gate for Reed-Muller (RM) logic circuit
implementation. To cope with the issues of the present AND and XOR cascaded AND/XOR …

[HTML][HTML] Design and implementation of hybrid logic based MAC unit using 45 nm technology

A Laxman, NSS Reddy, BR Naik - e-Prime-Advances in Electrical …, 2023 - Elsevier
Digital signal processing algorithms, at times, necessitate the execution of a substantial
quantity of mathematical operations to speed up and iterate upon a particular data set …

Ultra low-power high-speed single-bit hybrid full adder circuit

M Kumar, RK Baghel - 2017 8th International Conference on …, 2017 - ieeexplore.ieee.org
In this paper a low power hybrid 1-bit full adder circuit is designed and extended for 4 bit
ripple carry adder (RCA). A new XNOR logic is designed using complimentary-metal-oxide …