Double-gate junctionless 1T DRAM with physical barriers for retention improvement
MHR Ansari, N Navlakha, JY Lee… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
In this article, a double-gate (DG) junction-less (JL) transistor with physical barriers is
proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this …
proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this …
L-shaped tunnel field-effect transistor-based 1T DRAM with improved read current ratio, retention time, and sense margin
In this article, an L-shaped tunnel field-effect transistor (LTFET)-based one-transistor
dynamic random access memory (1T DRAM) with SiGe storage region was demonstrated …
dynamic random access memory (1T DRAM) with SiGe storage region was demonstrated …
A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance
A polycrystalline-silicon (poly-Si) dual-gate MOSFET-based one-transistor dynamic random-
access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier …
access memory (1T-DRAM) cell was developed using grain boundary (GB)-induced barrier …
Retention and scalability perspective of sub-100-nm double gate tunnel FET DRAM
N Navlakha, JT Lin, A Kranti - IEEE Transactions on Electron …, 2017 - ieeexplore.ieee.org
This paper reports on the design optimization of double gate (DG) tunnel FET (TFET) for
dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral …
dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral …
Doping dependent assessment of accumulation mode and junctionless FET for 1T DRAM
MHR Ansari, N Navlakha, JT Lin… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper demonstrates the use of double-gate accumulation mode (AM) and junctionless
(JL) transistors for dynamic memory applications at 85° C. The doping dependent …
(JL) transistors for dynamic memory applications at 85° C. The doping dependent …
1T-DRAM with shell-doped architecture
MHR Ansari, N Navlakha, JT Lin… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor
architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD …
architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD …
Dopingless 1T DRAM: Proposal, design, and analysis
A James, S Saurabh - IEEE Access, 2019 - ieeexplore.ieee.org
In this paper, we have proposed a dopingless 1T DRAM (DL-DRAM) that utilizes the charge
plasma concept. The proposed device employs a misaligned double-gate architecture to …
plasma concept. The proposed device employs a misaligned double-gate architecture to …
Capacitorless 2T-DRAM for higher retention time and sense margin
MHR Ansari, J Singh - IEEE Transactions on Electron Devices, 2020 - ieeexplore.ieee.org
This article showcases a junctionless (JL)/accumulation mode (AM) transistor connected
with an access JL transistor-based capacitorless dynamic random access memory (2T …
with an access JL transistor-based capacitorless dynamic random access memory (2T …
Design and analysis of dopingless 1T DRAM using work function engineered tunnel field effect transistors
AV Arun, PS Sreelekshmi, J Jacob - Microelectronics Journal, 2022 - Elsevier
In this paper, a dopingless DRAM based on work function engineered Tunnel field effect
transistor is proposed. Gate metal workfunction engineering is done to enhance ON/OFF …
transistor is proposed. Gate metal workfunction engineering is done to enhance ON/OFF …
Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability
N Navlakha, A Kranti - Nanotechnology, 2017 - iopscience.iop.org
The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate
as dynamic memory at 85 C with an enhanced sense margin (SM). Two symmetric gates …
as dynamic memory at 85 C with an enhanced sense margin (SM). Two symmetric gates …