[HTML][HTML] A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays

W Wang, X Li, L Chen, H Sun, F Zhang - Sensors, 2024 - mdpi.com
Aerospace-grade SRAM-based field-programmable gate arrays (FPGAs) used in space
applications are highly susceptible to single event effects, leading to soft errors in FPGAs …

Low overhead optimal parity codes

N Koppala, C Subhas - … Computing Electronics and Control), 2022 - telkomnika.uad.ac.id
The error detecting and correcting codes are used in critical applications like in intensive
care units, defense applications, and require highly reliable data. This brief focuses on …

Half diagonal matrix codes for reliable embedded memories

K Neelima, C Subhas - International journal of health sciences, 2022 - neliti.com
Reliability of embedded memories is dependent on at-speed rated correction capability of
error detection and correction codes. Many critical applications like medical databases …

An Improved Single and Double-Adjacent Error Correcting Codec with Lower Decoding Overheads

RK Maity, J Samanta, J Bhaumik - Journal of Signal Processing Systems, 2023 - Springer
Abstract Importance of Error Correcting Codes (ECCs) is increasing rapidly for protecting
memories from localized errors. These localized errors in memories are mainly due to …

Efficient adjacent 3D parity error detection and correction codes for embedded memories

K Neelima, C Subhas - 2020 IEEE International Conference on …, 2020 - ieeexplore.ieee.org
The detection and correction of errors during memory read operation performed per clock
cycle play a significant role in at-speed testing of embedded memories. The majority of key …

Construction Technique and Evaluation of High Performance -bit Burst Error Correcting Codes for Protecting MCUs

RK Maity, J Samanta, J Bhaumik - Journal of Circuits, Systems and …, 2023 - World Scientific
The occurrences of Multiple Cell Upset (MCU) are more liable to arise in modern memory
systems with the continuous upgradation of microelectronics technology from micron to deep …

OPCoSA: an Optimized Product Code for space applications

D Freitas, J Silveira, C Marcon, L Naviner, J Mota - Integration, 2022 - Elsevier
The integrated circuit shrinkage increases the probability and the number of errors in
memories due to the increase in the sensitivity to electromagnetic radiation. Critical …

Modified single error correction orthogonal latin square scheme to reduce parity check bits

RA Ahmed - Microprocessors and Microsystems, 2022 - Elsevier
Single-error correction (SEC) codes play a critical role in ensuring cache reliability. In ultra-
high-speed caches, decoding delay is a key element to consider when selecting an SEC …

[HTML][HTML] Modified Proficient Adjacent Error Correcting Codes

K Neelima, C Subhas - e-Prime-Advances in Electrical Engineering …, 2023 - Elsevier
As the technology scales down, the soft errors manifested from faults appear in memories
due to radiation effects. This paper suggests two decoding mechanisms using hamming bits …

Accelerating Columnar Storage Based on Asynchronous Skipping Strategy

W Li, Z Yang, L Deng, Z Cheng, W Wen, Y He - Big Data Research, 2023 - Elsevier
Many database applications, such as OnLine Analytical Processing (OLAP), web-based
information extraction or scientific computation, need to select a subset of fields based on …