Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation

AK Rajput, M Pattanaik - Microelectronics Journal, 2023 - Elsevier
Memory reliability is a critical issue in SRAM-based In-Memory Computing (IMC)
architecture. The rapid advance in transistor technology makes SRAM more sensitive to soft …

An energy-efficient computing-in-memory (CiM) scheme using field-free spin-orbit torque (SOT) magnetic RAMs

B Wu, H Zhu, D Reis, Z Wang, Y Wang… - … on Emerging Topics …, 2023 - ieeexplore.ieee.org
The separation of memory and computing units in the von Neumann architecture leads to
undesirable energy consumption due to data movement and insufficient memory bandwidth …

An energy efficient in-memory computing architecture using reconfigurable magnetic logic circuits for big data processing

MA Gargari, N Eslami… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
In-memory computing (IMC) is considered one of the most promising candidates to solve the
nontraditional challenges conventional computing systems face in dealing with novel big …

In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays

Y Hui, Q Li, L Wang, C Liu, D Zhang… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
In-memory computing represents an efficient paradigm for high-performance computing
using crossbar arrays of emerging nonvolatile devices. While various techniques have …

A Reconfigurable Non-Volatile Memory Architecture for Prolonged Wearable Health Monitoring Devices

MA Gargari, N Eslami… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Wearable devices have broadened the horizons of healthcare systems within consumer
digital products. However, these devices have limited power resources, emphasizing the …

Nonvolatile logic gate and full adder based on tri-terminal oxide resistive switching devices

J Cao, J Ye, T Wang, Y Ding, R Cheng, D Liu… - Microelectronic …, 2025 - Elsevier
Today's on-chip computing power is constrained by the “memory wall” and “power wall”
caused by the Von Neumann bottleneck. As a potential solution, this work has developed …

Neural network detector with sparse codes for spin transfer torque magnetic random access memory

CD Nguyen - Cogent Engineering, 2023 - Taylor & Francis
This paper presents leveraging the neural network detector to improve the performance of a
spin transfer torque magnetic random-access memory (STT-MRAM), where the sparse …

Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays

Y Hui, Q Li, C Liu, D Zhang… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The recently developed logic-in-memory offers a high-performance and energy-efficient
paradigm based on crossbar arrays of emerging non-volatile devices. However, the low …

Error Detection and Correction for Processing in Memory (PiM)

H Cılasun, S Resch, ZI Chowdhury, M Zabihi… - arXiv preprint arXiv …, 2022 - arxiv.org
Processing in memory (PiM) represents a promising computing paradigm to enhance
performance and/or energy efficiency of numerous emerging data-intensive applications …

[PDF][PDF] 基于电压调控自旋轨道矩器件多数决定逻辑门的存内华莱士树乘法器设计

惠亚娟, 李青朕, 王雷敏, 刘成 - Journal of Electronics & Information …, 2022 - jeit.ac.cn
在使用新型非易失性存储阵列进行存内计算的研究中, 存内乘法器的延迟往往随着位宽的增加呈
指数增长, 严重影响计算性能. 该文设计一种电压调控自旋轨道矩磁随机存储器(VGSOT-MRAM) …