[图书][B] VLSI test principles and architectures: design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …
design a testable and quality product, drive down test cost, improve product quality and …
Embedded deterministic test
J Rajski, J Tyszer, M Kassab… - IEEE transactions on …, 2004 - ieeexplore.ieee.org
This paper presents a novel test-data volume-compression methodology called the
embedded deterministic test (EDT), which reduces manufacturing test cost by providing one …
embedded deterministic test (EDT), which reduces manufacturing test cost by providing one …
Survey of test vector compression techniques
NA Touba - IEEE Design & test of computers, 2006 - ieeexplore.ieee.org
Test data compression consists of test vector compression on the input side and response,
compaction on the output side. This vector compression has been an active area of …
compaction on the output side. This vector compression has been an active area of …
[图书][B] Electronic design automation: synthesis, verification, and test
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
Estimating 3D hand pose from a cluttered image
V Athitsos, S Sclaroff - 2003 IEEE Computer Society …, 2003 - ieeexplore.ieee.org
A method is proposed that can generate a ranked list of plausible three-dimensional hand
configurations that best match an input image. Hand pose estimation is formulated as an …
configurations that best match an input image. Hand pose estimation is formulated as an …
[图书][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
Embedded deterministic test for low cost manufacturing test
J Rajski, J Tyszer, M Kassab… - Proceedings …, 2002 - ieeexplore.ieee.org
This paper introduces embedded deterministic test (EDT) technology, which reduces
manufacturing test cost by providing one to two orders of magnitude reduction in scan test …
manufacturing test cost by providing one to two orders of magnitude reduction in scan test …
An efficient test vector compression scheme using selective Huffman coding
A Jas, J Ghosh-Dastidar, ME Ng… - IEEE transactions on …, 2003 - ieeexplore.ieee.org
This paper presents a compression/decompression scheme based on selective Huffman
coding for reducing the amount of test data that must be stored on a tester and transferred to …
coding for reducing the amount of test data that must be stored on a tester and transferred to …
Enabling smart urban surveillance at the edge
The unprecedented urbanization and the staggering development of modern information
and communication technologies (ICT) demonstrate that the concept of Smart City is …
and communication technologies (ICT) demonstrate that the concept of Smart City is …
Variable-length input Huffman coding for system-on-a-chip test
PT Gonciari, BM Al-Hashimi… - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
This paper presents a new compression method for embedded core-based system-on-a-
chip test. In addition to the new compression method, this paper analyzes the three test data …
chip test. In addition to the new compression method, this paper analyzes the three test data …