A gate exhaustive test set applies all possible input combinations to each gate in a
combinational circuit, and observes the gate response at an observation point such as a …

The demand for higher quality requires more effective testing to filter out the bad devices. It
is already known that multi-detection of single stuck-at faults results in more fortuitous …

This paper evaluates N-detect scan ATPG patterns for their impact to test quality through
simulation and fallout from production on a Pentium 4 processor using 90 nm manufacturing …

Production test data from more than 500,000 chips is analyzed to understand the correlation
between the number of defective chips detected by a set of test patterns and the coverage …

This paper presents an iterative diagnosis test generation framework to improve logic fault
diagnosis resolution. Industrial examples are presented in this paper on how additional …

We present nGFSIM, a GPU-based fault simulator for stuck-at faults which can report the
fault coverage of one-to n-detection for any specified integer n using only a single run of fault …

Achieving Serendipitous N-detect Mark-Offs in Multi-Capture-Clock Scan Patterns Page 1
Paper 30.2 INTERNATIONAL TEST CONFERENCE 1 1-4244-1128-9/07/$25.00 © 2007 IEEE …

Simulated annealing is a powerful optimization technique based on the annealing
phenomenon in crystallization. In this paper we propose a simulated sintering technique …

With shrinking feature sizes of manufacturing processes, the occurrence of systematic
defects is expected to increase. In this paper, we present techniques for identifying potential …

Multiple-detect test sets detect single stuck line faults multiple times, and thus have a higher
probability of detecting complex defects. But current definitions of what constitutes a new test …