High-level power modeling, estimation, and optimization

E Macii, M Pedram, F Somenzi - Proceedings of the 34th annual Design …, 1997 - dl.acm.org
In the past, the major concern of the VLSI designers werearea, performance, cost, and
reliability. In recent years, however, this has changed and, increasingly, power is beinggiven …

[图书][B] The VLSI handbook

WK Chen - 1999 - taylorfrancis.com
Over the years, the fundamentals of VLSI technology have evolved to include a wide range
of topics and a broad range of practices. To encompass such a vast amount of knowledge …

System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip

T Givargis, F Vahid, J Henkel - IEEE/ACM International …, 2001 - ieeexplore.ieee.org
Provides a technique for efficiently exploring the configuration space of a parameterized
system-on-a-chip (SOC) architecture to find all Pareto-optimal configurations. These …

[图书][B] Low-power electronics design

C Piguet - 2018 - books.google.com
The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …

Power macromodeling for high level power estimation

S Gupta, FN Najm - Proceedings of the 34th annual Design Automation …, 1997 - dl.acm.org
A modeling approach is presentedthat captures the dependence of the power dissipationof
a combinational logic circuit on its input/outputsignal switching activity. The resultingpower …

[图书][B] Decision diagram techniques for micro-and nanoelectronic design handbook

SN Yanushkevich, DM Miller, VP Shmerko… - 2018 - taylorfrancis.com
Decision diagram (DD) techniques are very popular in the electronic design automation
(EDA) of integrated circuits, and for good reason. They can accurately simulate logic design …

Reliability analysis of logic circuits

MR Choudhury, K Mohanram - IEEE Transactions on Computer …, 2009 - ieeexplore.ieee.org
Reliability of logic circuits is emerging as an important concern in scaled electronic
technologies. Reliability analysis of logic circuits is computationally complex because of the …

Power modeling for high-level power estimation

S Gupta, FN Najm - IEEE Transactions on Very Large Scale …, 2000 - ieeexplore.ieee.org
In this paper, we propose a modeling approach that captures the dependence of the power
dissipation of a combinational logic circuit on its input/output signal switching statistics. The …

Regression-based RTL power modeling

A Bogliolo, L Benini, G De Micheli - ACM Transactions on Design …, 2000 - dl.acm.org
Register-transfer level (RTL) power estimation is a key feature for synthesis-based design
flows. The main challenge in establishing a sound RTL power estimation methodology is the …

High-level area and power estimation for VLSI circuits

M Nemani, FN Najm - … on Computer-Aided Design of Integrated …, 1999 - ieeexplore.ieee.org
High-level power estimation, when given only a high-level design specification such as a
functional or register-transfer level (RTL) description, requires high-level estimation of the …