Performance improvement of stencil computations for multi-core architectures based on machine learning

V Martínez, F Dupros, M Castro, P Navaux - Procedia Computer Science, 2017 - Elsevier
Stencil computations are the basis to solve many problems related to Partial Differential
Equations (PDEs). Obtaining the best performance with such numerical kernels is a major …

Online sharing-aware thread mapping in software transactional memory

DP Pasqualin, M Diener, AR Du Bois… - 2020 IEEE 32nd …, 2020 - ieeexplore.ieee.org
Software Transactional Memory (STM) is an alternative abstraction to synchronize
processes in parallel programming. One advantage is simplicity since it is possible to …

Self-tuning Intel restricted transactional memory

N Diegues, P Romano - Parallel Computing, 2015 - Elsevier
Abstract The Transactional Memory (TM) paradigm aims at simplifying the development of
concurrent applications by means of the familiar abstraction of atomic transaction. After a …

Improving performance of transactional memory through machine learning

Y Xiao, T Jeyakumaran, E Atoofian… - Concurrency and …, 2018 - Wiley Online Library
Transactional memory (TM) is a programming paradigm that facilitates parallel programming
for multi‐core processors. In the last few years, some chip manufacturers provided hardware …

Thread affinity in software transactional memory

DP Pasqualin, M Diener, AR Du Bois… - … on Parallel and …, 2020 - ieeexplore.ieee.org
Software Transactional Memory (STM) is an abstraction to synchronize accesses to shared
resources. It simplifies parallel programming by replacing the use of explicit locks and …

Characterizing the sharing behavior of applications using software transactional memory

DP Pasqualin, M Diener, AR Du Bois… - International Symposium …, 2020 - Springer
Abstract Software Transactional Memory (STM) is an alternative abstraction for process
synchronization in parallel programming. It is often easier to use than locks, avoiding issues …

An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory

N Zhou, G Delaval, B Robu, É Rutten… - Concurrency and …, 2018 - Wiley Online Library
A parallel program needs to manage the trade‐off between the time spent in synchronisation
and computation. This trade‐off is significantly affected by its parallelism degree. A high …

Self-tuning in distributed transactional memory

M Couceiro, D Didona, L Rodrigues… - … , Algorithms, Tools, and …, 2015 - Springer
Many different mechanisms have been developed to implement Distributed Transactional
Memory (DTM). Unfortunately, there is no “one-size-fits-all” design that offers the desirable …

Online tuning of parallelism degree in parallel nesting transactional memory

J Zeng, P Romano, J Barreto… - 2018 IEEE …, 2018 - ieeexplore.ieee.org
This paper addresses the problem of self-tuning the parallelism degree in Transactional
Memory (TM) systems that support parallel nesting (PN-TM). This problem has been long …

Thread and Data Mapping in Software Transactional Memory: An Overview

DP Pasqualin, M Diener, ARD Bois, ML Pilla - arXiv preprint arXiv …, 2022 - arxiv.org
In current microarchitectures, due to the complex memory hierarchies and different latencies
on memory accesses, thread and data mapping are important issues to improve application …