A memory system includes logical banks divided into sub-banks or collections of sub-banks.
The memory system responds to memory-access requests (eg, read and write) directed to a …

A micro-threaded memory device. A plurality of storage banks are provided, each including
a plurality of rows of storage cells and having an access restriction in that at least a minimum …

(57) ABSTRACT A memory system includes a master device. Such as a graphics controller
or processor, and an integrated circuit memory device operable in dynamic memory bank …

A fully-integrated 8.4 Gb/s 2.5 pJ/b mobile memory I/O transceiver using simultaneous
bidirectionaldual band signaling is presented. Incorporating both RF-band and baseband …

This paper presents a dual-loop two-step ZQ calibration scheme with a 20-nm DRAM
process to support dedicated supply voltages (and). The proposed calibration scheme …

An integrated circuit memory device has a storage array with an adjustable number of
memory banks, a row of sense ampli fiers to access storage cells in the storage array; and …

We present a sensing scheme with local bitline sense amplifier (L-BLSA) for sub-1V DRAM
core operation, which activates a low-Vt latch locally in time, the same as [1] but shares a …

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Flannagan et al. 5,787,267 A 7/1998 Leung et al. 4,700,328 A 10/1987 Burghard 5,793,998 …

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Statistical link analysis methods were previously developed for effective computation of bit
error rate due to intersymbol interference (ISI). In addition to ISI, supply voltage fluctuations …