Radiation testing of a multiprocessor macrosynchronized lockstep architecture with FreeRTOS

PM Aviles, A Lindoso, JA Belloch… - … on Nuclear Science, 2021 - ieeexplore.ieee.org
Nowadays, high-performance microprocessors are demanded in many fields, including
those with high-reliability requirements. Commercial microprocessors present a good …

A hybrid fault-tolerant LEON3 soft core processor implemented in low-end SRAM FPGA

A Lindoso, L Entrena… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end
FPGA (Artix-7) and evaluated its error detection capabilities through neutron irradiation and …

HETA: Hybrid error-detection technique using assertions

JR Azambuja, M Altieri, J Becker… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
This paper presents HETA, a hybrid technique based on assertions and a non-intrusive
enhanced watchdog module to detect SEE faults in microprocessors. These types of faults …

Selective SWIFT-R: A flexible software-based technique for soft error mitigation in low-cost embedded systems

F Restrepo-Calle, A Martínez-Álvarez… - Journal of Electronic …, 2013 - Springer
Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due
to their programmability and cost-effectiveness. Recent advances in electronic technologies …

Dual-core lockstep enhanced with redundant multithread support and control-flow error detection

M Peña-Fernández, A Serrano-Cases, A Lindoso… - Microelectronics …, 2019 - Elsevier
This work presents a new Dual-Core LockStep approach to enhance fault tolerance in
microprocessors. The proposed technique is based on the combination of software-based …

Evaluating neutron induced SEE in SRAM-based FPGA protected by hardware-and software-based fault tolerant techniques

JR Azambuja, G Nazar, P Rech, L Carro… - … on Nuclear Science, 2013 - ieeexplore.ieee.org
This paper presents an approach to detect SEEs in SRAM-based FPGAs by using software-
based techniques combined with a nonintrusive hardware module. We implemented a MIPS …

Evaluating selective redundancy in data-flow software-based techniques

E Chielle, JR Azambuja, RS Barth… - … on Nuclear Science, 2013 - ieeexplore.ieee.org
This paper presents an analysis of the efficiency of using selective redundancy applied to
registers in software-based techniques. The proposed selective redundancy chooses a set …

A new hybrid nonintrusive error-detection technique using dual control-flow monitoring

L Parra, A Lindoso, M Portela-Garcia… - … on Nuclear Science, 2014 - ieeexplore.ieee.org
Hybrid error-detection techniques combine software techniques with an external hardware
module that monitors the execution of a microprocessor. The external hardware module …

PTM-based hybrid error-detection architecture for ARM microprocessors

M Peña-Fernandez, A Lindoso, L Entrena… - Microelectronics …, 2018 - Elsevier
This work presents a hybrid error detection architecture that uses ARM PTM trace interface
to observe ARM microprocessor behaviour. The proposed approach is suitable for COTS …

Parallel processor architecture with a new algorithm for simultaneous processing of mips-based series instructions

A Hadizadeh, E Tanghatari - Emerging Science Journal, 2017 - ijournalse.org
Processors are main part of the calculation and decision making of a system. Today, due to
the increasing need of industry and technology to faster and more accurate computing …