A Lindoso, L Entrena… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end FPGA (Artix-7) and evaluated its error detection capabilities through neutron irradiation and …
This paper presents HETA, a hybrid technique based on assertions and a non-intrusive enhanced watchdog module to detect SEE faults in microprocessors. These types of faults …
Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies …
This work presents a new Dual-Core LockStep approach to enhance fault tolerance in microprocessors. The proposed technique is based on the combination of software-based …
This paper presents an approach to detect SEEs in SRAM-based FPGAs by using software- based techniques combined with a nonintrusive hardware module. We implemented a MIPS …
E Chielle, JR Azambuja, RS Barth… - … on Nuclear Science, 2013 - ieeexplore.ieee.org
This paper presents an analysis of the efficiency of using selective redundancy applied to registers in software-based techniques. The proposed selective redundancy chooses a set …
Hybrid error-detection techniques combine software techniques with an external hardware module that monitors the execution of a microprocessor. The external hardware module …
M Peña-Fernandez, A Lindoso, L Entrena… - Microelectronics …, 2018 - Elsevier
This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observe ARM microprocessor behaviour. The proposed approach is suitable for COTS …
Processors are main part of the calculation and decision making of a system. Today, due to the increasing need of industry and technology to faster and more accurate computing …