In recent years, it has been witnessed that the systolic array is a successful architecture for
DNN hardware accelerators. However, the design of systolic arrays also encountered many …

In recent years, many accelerators have been proposed to efficiently process sparse tensor
algebra applications (eg, sparse neural networks). However, these proposals are single …

Sparsity is a growing trend in modern DNN models. Existing Sparse-Sparse Matrix
Multiplication (SpMSpM) accelerators are tailored to a particular SpMSpM dataflow (ie, Inner …

Over the past few years, the explosion in sparse tensor algebra workloads has led to a
corresponding rise in domain-specific accelerators to service them. Due to the irregularity …

Nowadays, always-on intelligent and self-powered visual perception systems have gained
considerable attention and are widely used. However, capturing data and analyzing it via a …

Running multiple deep neural networks (DNNs) in parallel has become an emerging
workload in both edge devices, such as mobile phones where multiple tasks serve a single …

This work paves the way to realize a processing-in-pixel (PIP) accelerator based on a
multilevel HfOx resistive random access memory (RRAM) as a flexible, energy-efficient, and …

The combination of pre-trained models and task-specific fine-tuning schemes, such as
BERT, has achieved great success in various natural language processing (NLP) tasks …

Edge computing devices inherently face tight resource constraints, which is especially
apparent when deploying Deep Neural Networks (DNN) with high memory and compute …

Convolutional neural networks are normally used in systems with dedicated neural
processing units for CNN-related computations. For high performance and low hardware …