Power-aware computing in wearable sensor networks: An optimal feature selection

H Ghasemzadeh, N Amini, R Saeedi… - IEEE Transactions …, 2014 - ieeexplore.ieee.org
Wearable sensory devices are becoming the enabling technology for many applications in
healthcare and well-being, where computational elements are tightly coupled with the …

[图书][B] Embedded systems design: the ARTIST roadmap for research and development

B Bouyssounouse, J Sifakis - 2005 - books.google.com
Embedded systems now include a very large proportion of the advanced products designed
in the world, spanning transport (avionics, space, automotive, trains), electrical and …

Power consumption modeling and characterization of the TI C6201

N Julien, J Laurent, E Senn, E Martin - IEEE Micro, 2003 - ieeexplore.ieee.org
This new approach characterizes power dissipation on complex dsps. its processor model
relies on an initial functional-level power analysis of the target processor together with a …

Adres & dresc: Architecture and compiler for coarse-grain reconfigurable processors

B Mei, M Berekovic, JY Mignolet - Fine-and coarse-grain reconfigurable …, 2007 - Springer
Nowadays, a typical embedded system requires high performance to perform tasks such as
video encoding/decoding at run-time. It should consume little energy to work hours or even …

Power modeling and characterization of computing devices

S Reda, AN Nowroz - Foundations and Trends® in Electronic …, 2012 - nowpublishers.com
In this survey we describe the main research directions in pre-silicon power modeling and
post-silicon power characterization. We review techniques in power modeling and …

Cache coherence tradeoffs in shared-memory MPSoCs

M Loghi, M Poncino, L Benini - ACM Transactions on Embedded …, 2006 - dl.acm.org
Shared memory is a common interprocessor communication paradigm for single-chip
multiprocessor platforms. Snoop-based cache coherence is a very successful technique that …

SoftExplorer: Estimating and optimizing the power and energy consumption of a C program for DSP applications

E Senn, J Laurent, N Julien, E Martin - EURASIP Journal on Advances in …, 2005 - Springer
We present a method to estimate the power and energy consumption of an algorithm directly
from the C program. Three models are involved: a model for the targeted processor (the …

Clustered loop buffer organization for low energy VLIW embedded processors

M Jayapala, F Barat, T Vander Aa… - IEEE Transactions …, 2005 - ieeexplore.ieee.org
Current loop buffer organizations for very large instruction word processors are essentially
centralized. As a consequence, they are energy inefficient and their scalability is limited. To …

Power breakdown analysis for a heterogeneous NoC platform running a video application

A Lambrechts, P Raghavan, A Leroy… - 2005 IEEE …, 2005 - ieeexplore.ieee.org
Users expect future handheld devices to provide extended multimedia functionality and
have long battery life. This type of application imposes heavy constraints on performance …

[图书][B] Ultra-low energy domain-specific instruction-set processors

F Catthoor, P Raghavan, A Lambrechts, M Jayapala… - 2010 - books.google.com
Modern consumers carry many electronic devices, like a mobile phone, digital camera, GPS,
PDA and an MP3 player. The functionality of each of these devices has gone through an …