An optimal gate design for the synthesis of ternary logic circuits

S Kim, T Lim, S Kang - 2018 23rd Asia and South Pacific …, 2018 - ieeexplore.ieee.org
Over the last few decades, CMOS-based digital circuits have been steadily developed.
However, because of the power density limits, device scaling may soon come to an end, and …

A novel ternary multiplier based on ternary CMOS compact model

Y Kang, J Kim, S Kim, S Shin, ES Jang… - 2017 IEEE 47th …, 2017 - ieeexplore.ieee.org
Multiple-valued logic (MVL) has potential advantages for energy-efficient design by reducing
a circuit complexity. Because of physical device and circuit realization issues, however …

Arithmetic with binary-encoded balanced ternary numbers

B Parhami, M McKeown - 2013 Asilomar Conference on …, 2013 - ieeexplore.ieee.org
Ternary number representation and arithmetic, based on the radix-3 digit set {-1, 0,; 1}, has
been studied at various times in the history of digital computing. Some such studies …

Extreme low power technology using ternary arithmetic logic circuits via drastic interconnect length reduction

K Kim, S Kim, Y Lee, D Kim, SY Kim… - 2020 IEEE 50th …, 2020 - ieeexplore.ieee.org
Ternary logic is more power-efficient than binary logic because of lower device count
required to perform the same logic functions. Its benefits become more pronounced in highly …

Truncated ternary multipliers

B Parhami - IET Computers & Digital Techniques, 2015 - Wiley Online Library
Balanced ternary number representation and arithmetic, based on the symmetric radix‐3
digit set {− 1, 0,+ 1}, has been studied at various times in the history of computing. Among …

[HTML][HTML] Design and Simulation of Balanced Ternary Priority Encoder

AG Goenka, S Mitra, H Maheshwari, N Das - Memories-Materials, Devices …, 2024 - Elsevier
The priority encoder is a frequently used circuit in binary logic and is mostly used for
interrupt handling and other priority resolving tasks. On the other hand, Ternary computing …

[PDF][PDF] Aspect of balanced ternary arithmetic implemented using CMOS recharged semi-floating gate device

H Gundersen - Oslo: Oslo University, 2008 - researchgate.net
Mostly all electronics used in computers today are based on binary logic. However, does the
binary logic have the capacity to be the leading technology in the future? Thus I raise the …

Design of balanced ternary encoder and decoder

AG Goenka, S Mitra, N Das - 2022 6th International …, 2022 - ieeexplore.ieee.org
The origin of Ternary computing which is based on a 3-valued logic, can be traced back to
the 18 th century. Despite having its enormous potential to deal with a huge range of …

Partial product generation for unbalanced ternary signed multiplication

SD Mohammadi, RF Mirzaee… - International Journal of …, 2019 - inderscienceonline.com
Signed multiplication is an essential operation in computer arithmetic. The first step of
multiplication is called partial product generation. Partial products are simply generated in …

[PDF][PDF] Realization of ternary sigma-delta modulated arithmetic processing modules

AZ Sadik, PJ O'Shea - EURASIP Journal on Advances in Signal …, 2009 - Springer
Sigma-delta modulated systems have a number of very appealing properties and are,
therefore, heavily used in analog to digital converters, amplifiers, and modulators. This …