BACKGROUND Different instruction issue modes have different power and performance
trade-offs. Processors with logic units implementing in-order instruction issue modes issue …

7,873,820 B2 2002/01783.50 A1 2003. O163679 A1 2004/O123075 A1 2004/O193858 A1
2005, OO15537 A1* 2006/0095750 A1 2006/010.7028 A1 2006/0242394 A1 …

In a normal, non-loop mode a uOp buffer receives and stores for dispatch the uOps
generated by a decode stage based on a received instruction sequence. In response to …

US PATENT DOCUMENTS unit detects a backwards taken branch and starts tracking the
5,303.357 A 4, 1994 Inoue et al. loop candidate. The control unit tracks taken branches of …

BACKGROUND A compiler accepts as input a source code in a high-level programming
language or some other equivalent high level semantic representation of a computer …

Microprocessors typically may include components that manages detection and execution of
instruction loops. A microprocessor may detect Small-sized loops with a large number of …

(Continued) Primary Examiner—Joseph P Hirl Assistant Examiner—J. Brant Murphy
ABSTRACT An execution flow protection module (30) for a microcon troller (10) with a …

Description of the Related Art Before being executed by a processor, instructions are
frequently stored in a cache. As an instruction stream is executed, the cache may be …

Methods, apparatuses, and processors for packing multiple iterations of a loop in a loop
buffer. A loop candidate that meets the criteria for buffering is detected in the instruction …

In a first example, a non-transitory machine-readable medium includes a compiler that
detects a soft-break indicator in a loop included in source code and the compiler applies …