Heterogeneous recovery in a redundant memory system
KC Gower, LA Lastras-Montano, PJ Meaney… - US Patent …, 2014 - Google Patents
BACKGROUND This invention relates generally to computer memory and more particularly,
to heterogeneous recovery in a redundant memory system. Redundant array of independent …
to heterogeneous recovery in a redundant memory system. Redundant array of independent …
Low-latency, frequency-agile clock multiplier
In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having
spectrally-staggered lock ranges are operated in parallel to effect a collective input …
spectrally-staggered lock ranges are operated in parallel to effect a collective input …
Homogeneous recovery in a redundant memory system
KC Gower, LA Lastras-Montano, PJ Meaney… - US Patent …, 2014 - Google Patents
Providing homogeneous recovery in a redundant memory system that includes a memory
controller, a plurality of memory channels in communication with the memory controller, an …
controller, a plurality of memory channels in communication with the memory controller, an …
Integrated circuit comprising circuitry to determine settings for an injection-locked oscillator
Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an
injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is …
injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is …
Low-latency, frequency-agile clock multiplier
CPC.............. H03K5/13 (2013.01); H03K5/00006 R i ected by the first and/or RSSR
(2013.01); H03L 7/06 (2013.01); H03L 7/0995 R E. 1. E. R 1nput clock 1s sists N le …
(2013.01); H03L 7/06 (2013.01); H03L 7/0995 R E. 1. E. R 1nput clock 1s sists N le …
Reception circuit and semiconductor integrated circuit
T Shibasaki, H Tamura - US Patent 9,191,187, 2015 - Google Patents
(57) ABSTRACT A burst mode CDR detects an edge from a data signal Super imposed with
a clock, and generates a recovered clock by means of a Voltage controlled oscillator whose …
a clock, and generates a recovered clock by means of a Voltage controlled oscillator whose …
Clock and data recovery circuit selectively configured to operate in one of a plurality of stages and related method thereof
WZ Chen, MC Su, YH Chen - US Patent 8,923,468, 2014 - Google Patents
An exemplary clock and data recovery circuit includes a serial data input node arranged for
receiving a serial data; a refer ence clock input node arranged for receiving a reference …
receiving a serial data; a refer ence clock input node arranged for receiving a reference …
Jitter-based clock selection
In a first clock frequency multiplier, multiple injection locked oscillators (ILOs) having
spectrally-staggered lock ranges are operated in parallel to effect a collective input …
spectrally-staggered lock ranges are operated in parallel to effect a collective input …
Homogeneous recovery in a redundant memory system
KC Gower, LA Lastras-Montano, PJ Meaney… - US Patent …, 2014 - Google Patents
BACKGROUND This invention relates generally to computer memory and more particularly,
to homogeneous recovery in a redundant memory system. Redundant array of independent …
to homogeneous recovery in a redundant memory system. Redundant array of independent …
Frequency-agile clock multiplier
In a first clock frequency multiplier, multiple injection locked oscillators (ILOS) having
spectrally-staggered lock ranges are operated in parallel to effect a collective input …
spectrally-staggered lock ranges are operated in parallel to effect a collective input …