Harpocrates: Breaking the silence of cpu faults through hardware-in-the-loop program generation

N Karystinos, O Chatzopoulos… - 2024 ACM/IEEE 51st …, 2024 - ieeexplore.ieee.org
Several hyperscalers have recently disclosed the occurrence of Silent Data Corruptions
(SDCs) in their systems fleets, sparking concerns about the severity of known and the …

Systematic software-based self-test for pipelined processors

D Gizopoulos, M Psarakis, M Hatzimihail… - … Transactions on Very …, 2008 - ieeexplore.ieee.org
Software-based self-test (SBST) has recently emerged as an effective methodology for the
manufacturing test of processors and other components in systems-on-chip (SoCs). By …

Simulation-based functional test generation for embedded processors

CHP Wen, LC Wang, KT Cheng - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
Deterministic functional test pattern generation has been a long-standing open problem,
which is an important problem to be solved for both design verification and manufacturing …

Systematic software-based self-test for pipelined processors

M Psarakis, D Gizopoulos, M Hatzimihail… - Proceedings of the 43rd …, 2006 - dl.acm.org
Software-based self-test (SBST) has recently emerged as an effective methodology for the
manufacturing test of processors and other components in Systems-on-Chip (SoCs). By …

Software-based self-testing with multiple-level abstractions for soft processor cores

CH Chen, CK Wei, TH Lu… - IEEE transactions on very …, 2007 - ieeexplore.ieee.org
Software-based self-test (SBST) is a promising approach for testing a processor core
embedded in a system-on-chip (SoC) system. Test routine development for SBST can be …

Satisfiability-based automatic test program generation and design for testability for microprocessors

L Lingappan, NK Jha - IEEE Transactions on Very Large Scale …, 2007 - ieeexplore.ieee.org
In this paper, we present a satisfiability (SAT)-based framework for automatically generating
test programs that target gate-level stuck-at faults in microprocessors. The microarchitectural …

Self-test libraries analysis for pipelined processors transition fault coverage improvement

R Cantoro, P Girard, R Masante… - 2021 IEEE 27th …, 2021 - ieeexplore.ieee.org
Testing digital integrated circuits is generally done using Design-for-Testability (DfT)
solutions. Such solutions, however, introduce non-negligible area and timing overheads that …

New perspectives on core in-field path delay test

R Cantoro, D Foti, S Sartoni, MS Reorda… - 2020 IEEE …, 2020 - ieeexplore.ieee.org
Path Delay fault test currently exploits DfT-based techniques, mainly relying on scan chains,
widely supported by commercial tools. However, functional testing may be a desirable …

Online periodic self-test scheduling for real-time processor-based systems dependability enhancement

D Gizopoulos - IEEE Transactions on Dependable and Secure …, 2009 - ieeexplore.ieee.org
Online periodic self-testing is a cost-effective technique to ensure correct operation of
microprocessor-based systems in the field and improve their dependability in the presence …

Self-test library generation for in-field test of path delay faults

L Anghel, R Cantoro, R Masante… - … on Computer-Aided …, 2023 - ieeexplore.ieee.org
New semiconductor technologies for advanced applications are more prone to defects and
imperfections related, among several different causes, to the manufacturing process, aging …