Analysis of critical thermal issues in 3D integrated circuits
Several key attributes of a 3D integrated chip structure are analyzed in this work. Critical
features related to the effect of the size of the substrate, heat sink, device layer, through …
features related to the effect of the size of the substrate, heat sink, device layer, through …
Non-uniform micro-channel design for stacked 3D-ICs
B Shi, A Srivastava, P Wang - Proceedings of the 48th Design …, 2011 - dl.acm.org
Micro-channel cooling shows great potential in removing high density heat in 3D circuits.
The current micro-channel heat sink designs spread the entire surface to be cooled with …
The current micro-channel heat sink designs spread the entire surface to be cooled with …
Optimized micro-channel design for stacked 3-D-ICs
B Shi, A Srivastava - … on Computer-Aided Design of Integrated …, 2013 - ieeexplore.ieee.org
The three dimensional circuit (3-D-IC) achieves high performance by stacking several layers
of active electronic components vertically. Despite its impact on performance improvement, 3 …
of active electronic components vertically. Despite its impact on performance improvement, 3 …
Scheduling tests for 3D stacked chips under power constraints
B SenGupta, U Ingelsson, E Larsson - Journal of electronic testing, 2012 - Springer
Abstract This paper addresses Test Application Time (TAT) reduction under power
constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs) …
constraints for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs) …
Thermal power plane for integrated circuits
H Barowski, T Brunschwiler, H Harrer, A Huber… - US Patent …, 2013 - Google Patents
A mechanism is provided for a thermal power plane that delivers power and constitutes
minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first …
minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first …
A novel approach for using TSVs as membrane capacitance in neuromorphic 3-D IC
An advanced neurophysiological computing system can incorporate a 3-D integration
system composed of emerging nano-scale devices to provide massive parallelism having …
system composed of emerging nano-scale devices to provide massive parallelism having …
Optimized semiconductor packaging in a three-dimensional stack
H Barowski, T Brunschwiler, H Harrer, A Huber… - US Patent …, 2012 - Google Patents
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Schuurman et al. 6,351,393 B1 2/2002 Kresge et al. 6,611,057 B2 8, 2003 Mikubo et al …
Schuurman et al. 6,351,393 B1 2/2002 Kresge et al. 6,611,057 B2 8, 2003 Mikubo et al …
Liquid cooling for 3D-ICs
B Shi, A Srivastava - 2011 International Green Computing …, 2011 - ieeexplore.ieee.org
Liquid cooling for 3D-ICs Page 1 Liquid Cooling for 3D-ICs Bing Shi and Ankur Srivastava
University of Maryland, College Park, MD, USA 1bingshi, ankursl@umd.edu 1 Introduction The …
University of Maryland, College Park, MD, USA 1bingshi, ankursl@umd.edu 1 Introduction The …
Cooling of 3D-IC using non-uniform micro-channels and sensor based dynamic thermal management
B Shi, A Srivastava - 2011 49th Annual Allerton Conference on …, 2011 - ieeexplore.ieee.org
The three dimensional integrated circuit (3D-IC) brings new challenges to chip thermal
management due to its high power density. Micro-channel based liquid cooling shows great …
management due to its high power density. Micro-channel based liquid cooling shows great …
[PDF][PDF] 可热扩展的三维并行散热集成方法: 用于大规模并行计算的片上系统关键技术
骆祖莹， 韩银和， 赵国兴， 余先川， 周明全 - 2011 - cjc.ict.ac.cn
摘要现有的三维(3D) 垂直集成技术无法实现热扩展, 受限于过高的温度, 难以通过众多器件层的
叠放来实现性能的最大化. 文中提出了一种具有热扩展性的3D 并行散热集成方法 …
叠放来实现性能的最大化. 文中提出了一种具有热扩展性的3D 并行散热集成方法 …