[图书][B] Electronic design automation: synthesis, verification, and test
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
Gate sizing to radiation harden combinational logic
Q Zhou, K Mohanram - … on Computer-Aided Design of Integrated …, 2005 - ieeexplore.ieee.org
A gate-level radiation hardening technique for cost-effective reduction of the soft error failure
rate in combinational logic circuits is described. The key idea is to exploit the asymmetric …
rate in combinational logic circuits is described. The key idea is to exploit the asymmetric …
Llms for relational reasoning: How far are we?
Large language models (LLMs) have revolutionized many areas (eg natural language
processing, software engineering, etc.) by achieving state-of-the-art performance on …
processing, software engineering, etc.) by achieving state-of-the-art performance on …
[图书][B] Design for manufacturability and statistical design: a constructive approach
Design for Manufacturability and Statistical Design: A Constructive Approach provides a
thorough treatment of the causes of variability, methods for statistical data characterization …
thorough treatment of the causes of variability, methods for statistical data characterization …
[图书][B] Advanced formal verification
R Drechsler - 2004 - Springer
Modern circuits may contain up to several hundred million transistors. In the meantime it has
been observed that verification becomes the major bottleneck in design flows, ie up to 80 …
been observed that verification becomes the major bottleneck in design flows, ie up to 80 …
Multi-level logic minimization using implicit don't cares
KA Bartlett, RK Brayton, GD Hachtel… - … on Computer-Aided …, 1988 - ieeexplore.ieee.org
An approach is described for the minimization of multilevel logic circuits. A multilevel
representation of a block of combinational logic is defined, called a Boolean network. A …
representation of a block of combinational logic is defined, called a Boolean network. A …
Reducing structural bias in technology mapping
S Chatterjee, A Mishchenko, RK Brayton… - … on Computer-Aided …, 2006 - ieeexplore.ieee.org
Technology mapping, based on directed acyclic graph covering, suffers from the problem of
structural bias: The structure of the mapped netlist depends strongly on the subject graph. In …
structural bias: The structure of the mapped netlist depends strongly on the subject graph. In …
[图书][B] Decision diagram techniques for micro-and nanoelectronic design handbook
SN Yanushkevich, DM Miller, VP Shmerko… - 2018 - taylorfrancis.com
Decision diagram (DD) techniques are very popular in the electronic design automation
(EDA) of integrated circuits, and for good reason. They can accurately simulate logic design …
(EDA) of integrated circuits, and for good reason. They can accurately simulate logic design …
Statistical timing analysis using bounds and selective enumeration
A Agarwal, D Blaauw, V Zolotov… - Proceedings of the 8th …, 2002 - dl.acm.org
The growing impact of within-die process variation has created the need for statistical timing
analysis, where gate delays are modeled as random variables. Statistical timing analysis …
analysis, where gate delays are modeled as random variables. Statistical timing analysis …
Cost-effective radiation hardening technique for combinational logic
Q Zhou, K Mohanram - IEEE/ACM International Conference on …, 2004 - ieeexplore.ieee.org
A radiation hardening technique for combinational logic circuits is described. The key idea is
to exploit the asymmetric logical masking probabilities of gates, hardening gates that have …
to exploit the asymmetric logical masking probabilities of gates, hardening gates that have …