Design Approaches of Ultra-Low Power SAR ADC for Biomedical Systems—A Review

K Aneesh, G Manoj, S Shylu Sam - Journal of Circuits, Systems and …, 2022 - World Scientific
In recent years, implantable biomedical devices like cardiac pacemaker, defibrillators,
cochlear implants, visual prosthesis etc. have gained immense importance in the personal …

A partially static high frequency 18t hybrid topological flip-flop design for low power application

AK Mishra, U Chopra… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
In this brief, an extremely low power true clocking flip-flop is proposed using eighteen
transistors only. The flip-flop is a synchronous bistable element that stores single-bit …

A variation-aware design for storage cells using Schottky-barrier-type GNRFETs

E Abbasian, M Gholipour - Journal of Computational Electronics, 2020 - Springer
Graphene nanoribbons (GNRs) are a good replacement material for silicon to overcome
short-channel effects in nanoscale devices. However, with continuous technology scaling …

Low-power retentive true single-phase-clocked flip-flop with redundant-precharge-free operation

H You, J Yuan, Z Yu, S Qiao - IEEE Transactions on Very Large …, 2021 - ieeexplore.ieee.org
As basic components, optimizing power consumption of flip-flops (FFs) can significantly
reduce the power of digital systems. In this article, an energy-efficient retentive true-single …

Design and analysis of ultra‐low power 18T adaptive data track flip‐flop for high‐speed application

A Kumar Mishra, D Vaithiyanathan… - International Journal of …, 2021 - Wiley Online Library
This paper proposes a novel master slave (MS) flip‐flop design achieved by using only 18
transistors with a single‐phase clock and mixed topology. This design has lowest …

A novel survey on ubiquitous computing

K Dhyani, S Bhachawat, J Prabhu… - Data Intelligence and …, 2022 - Springer
The rapid developments in IoT, wireless technology, and mobile computing devices imply
that ubiquitous computing is not a far-off dream from the present. But while it is not wrong to …

A power and delay efficient circuit for CMOS phase detector and phase frequency detector

S Valasa, JR Shinde, DR Ramji… - 2021 6th international …, 2021 - ieeexplore.ieee.org
Dynamic logic circuits are preferred over CMOS static logic circuits due to the low area and
high-speed advantage they offer in high-performance designs. In electronics circuits, the …

Sleepy CMOS-sleepy stack (SC-SS): a novel high speed, area and power efficient technique for VLSI circuit design

A Sharma, H Sohal, H Jit Kaur - Journal of Circuits, Systems and …, 2019 - World Scientific
This paper presents a novel ultra-low-power Sleepy CMOS-Sleepy Stack (SC-SS) technique
for nano scale VLSI technologies. Eight prior techniques are taken for comparison with …

[PDF][PDF] Performance analysis of non-identical master slave flip flops at 65nm node

U Chopra, AK Mishra, D Vaithiyanathan - Ijitee, 2019 - researchgate.net
This paper presents the performance analysis of the different master slave flip flop reported
and comparison of their parameters such as power, area, delay setup time and hold time. To …

Power consumption and delay comparison of a modified tcff with existing ff implemented using finfet and load test circuit analysis

D Vaithiyanathan, AK Mishra… - 2021 IEEE Madras …, 2021 - ieeexplore.ieee.org
In this paper a single phase clock flip-flop has been introduced. This is a modified version of
topologically compressed flip-flop. It consist of 19 transistors which is two transistor less than …