H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the
transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency …

Multi-mode non-return-to-zero (NRZ) and orthogonal dif ferential vector signaling (ODVS)
clock and data recovery circuits having configurable sub-channel multi-input com parator …

A pair of ground planes arranged in parallel, a dielectric medium disposed in between the
pair of ground planes, and a set of at least four signal conductors disposed in the dielectric …

H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the
transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency …

Methods and systems are described for receiving, at an input differential branch pair, a set of
input signals, and responsively generating a first differential current, receiving, at an input of …

Methods are described allowing a vector signaling code to encode multi-level data without
the significant alphabet size increase known to cause symbol dynamic range compression …

Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS)
clock and data recovery circuits having configurable sub-channel multi-input comparator …

Methods and systems are described for asynchronously measuring an equalized
information signal to obtain amplitude information, modifying frequency dependent …

Transmission of baseband and carrier-modulated vector codewords, using a plurality of
encoders, each encoder configured to receive information bits and to generate a set of …

Methods are described allowing a vector signaling code to encode multi-level data without
the significant alphabet size increase known to cause symbol dynamic range compres sion …