A 32 gb/s 0.55 mw/gbps pam4 1-fir 2-iir tap dfe receiver in 65-nm cmos
O Elhadidy, A Roshan-Zamir, HW Yang… - 2015 symposium on …, 2015 - ieeexplore.ieee.org
A PAM4 serial I/O receiver efficiently implements a decision feedback equalizer (DFE) that
employs 1-FIR and 2-IIR taps for first post-cursor and long-tail ISI cancellation, respectively …
employs 1-FIR and 2-IIR taps for first post-cursor and long-tail ISI cancellation, respectively …
Design of an on-interposer passive equalizer for high bandwidth memory (HBM) with 30Gbps data transmission
In this paper, a new on-interposer passive equalizer was proposed for the next generation
High Bandwidth Memory (HBM) with 1024 I/O lines and 30 Gbps data rate. It is a coil-shaped …
High Bandwidth Memory (HBM) with 1024 I/O lines and 30 Gbps data rate. It is a coil-shaped …
A 0.0375-pJ/bit Charge-Steering Based Hybrid for 8-Gb/s/pin Full-Duplex Chip-to-Chip Interconnects in 65-nm CMOS
PK Govindaswamy, N Wary… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This paper presents an energy-efficient, half-rate charge-steering logic (HR-CSL) based
echo cancellation hybrid (ECH) circuit topology for full-duplex (FD) signaling across chip-to …
echo cancellation hybrid (ECH) circuit topology for full-duplex (FD) signaling across chip-to …
New charge-steering DFEs in 55-nm CMOS
J Pike, M Parvizi, D Berton… - … on Circuits and …, 2020 - ieeexplore.ieee.org
New charge-steering DFEs are proposed and simulated in 55-nm CMOS for use in wireline
transceivers. Four new methods of applying DFE taps demonstrate significant power savings …
transceivers. Four new methods of applying DFE taps demonstrate significant power savings …
A low-power miniature 20 Gb/s passive/active hybrid equalizer in 90 nm CMOS
CC Lee, HC Hsieh, SSH Hsu - IEEE Microwave and Wireless …, 2015 - ieeexplore.ieee.org
In this letter, a compact and very low power passive/active hybrid equalizer is presented. By
sharing the loading of high frequency peaking with the active equalizing stage, the passive …
sharing the loading of high frequency peaking with the active equalizing stage, the passive …
A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects
PK Govindaswamy, N Wary… - … Symposium on Circuits …, 2022 - ieeexplore.ieee.org
In this paper, a low-power half-rate charge-steering echo cancellation hybrid circuit topology
is proposed for full-duplex signaling over chip-to-chip interconnects. The proposed half-rate …
is proposed for full-duplex signaling over chip-to-chip interconnects. The proposed half-rate …
Electronic apparatus
KO Baekseok - US Patent 11,184,199, 2021 - Google Patents
Disclosed is an electronic apparatus including: a substrate; and an integrated circuit (IC) and
an inductor provided in the substrate, the IC including: a plurality of subcircuits; and an …
an inductor provided in the substrate, the IC including: a plurality of subcircuits; and an …
Research and design on phase-locked loop and equalizer for wireline communications
Y You - 2015 - search.proquest.com
The rise of cloud computing and advanced network services like online video/audio has
continuously driven the demand for higher wireline communication bandwidth. It brings on …
continuously driven the demand for higher wireline communication bandwidth. It brings on …