Emerging NVM: A survey on architectural integration and research challenges

J Boukhobza, S Rubini, R Chen, Z Shao - ACM Transactions on Design …, 2017 - dl.acm.org
There has been a surge of interest in Non-Volatile Memory (NVM) in recent years. With
many advantages, such as density and power consumption, NVM is carving out a place in …

Architecture design with STT-RAM: Opportunities and challenges

P Chi, S Li, Y Cheng, Y Lu, SH Kang… - 2016 21st Asia and …, 2016 - ieeexplore.ieee.org
The emerging spin-transfer torque magnetic random-access memory (STT-RAM) has
attracted a lot of interest from both academia and industry in recent years. It has been …

AOS: Adaptive overwrite scheme for energy-efficient MLC STT-RAM cache

X Chen, N Khoshavi, J Zhou, D Huang… - Proceedings of the 53rd …, 2016 - dl.acm.org
Spin-Transfer Torque Random Access Memory (STT-RAM) has been identified as an
advantageous candidate for on-chip memory technology due to its high density and ultra low …

The emergence of the local moment molecular spin transistor

G Hao, R Cheng, PA Dowben - Journal of Physics: Condensed …, 2020 - iopscience.iop.org
Local moment molecular systems have now been used as the conduction channel in gated
spintronics devices, and some of these three terminal devices might even be considered …

Energy-aware adaptive restore schemes for MLC STT-RAM cache

X Chen, N Khoshavi, RF DeMara… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
For the sake of higher cell density while achieving near-zero standby power, recent research
progress in Magnetic Tunneling Junction (MTJ) devices has leveraged Multi-Level Cell …

Temperature impact analysis and access reliability enhancement for 1T1MTJ STT-RAM

B Wu, Y Cheng, J Yang… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Spin-transfer torque magnetic random access memory (STT-RAM) is a promising and
emerging technology due to its many advantageous features such as scalability …

Reliable nonvolatile memories: Techniques and measures

S Swami, K Mohanram - IEEE Design & Test, 2017 - ieeexplore.ieee.org
Reliability continues to be a severe challenge in the development of emerging memories. In
this article, the authors offer a comprehensive survey of reliability enhancement techniques …

TA-LRW: A replacement policy for error rate reduction in STT-MRAM caches

E Cheshmikhani, H Farbeh… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
As technology process node scales down, on-chip SRAM caches lose their efficiency
because of their low scalability, high leakage power, and increasing rate of soft errors …

Data block manipulation for error rate reduction in STT-MRAM based main memory

N Mahdavi, F Razaghian, H Farbeh - The Journal of Supercomputing, 2022 - Springer
Downscaling of semiconductor technology has led DRAM-based main memories to lag
behind emerging non-volatile memories, eg, Spin-Transfer Torque Magnetic Random …

3RSeT: Read disturbance rate reduction in STT-MRAM caches by selective tag comparison

E Cheshmikhani, H Farbeh… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Recent development in memory technologies has introduced Spin-Transfer Torque
Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip …