Auto-tuner-based controller for quadcopter attitude tracking applications

SK Kim, CK Ahn - IEEE Transactions on Circuits and Systems II …, 2019 - ieeexplore.ieee.org
This brief offers a nonlinear advanced attitude tracking controller for quadcopter
applications. The proposed technique incorporates an auto-tuner and disturbance observers …

Self-tuning position-tracking controller for two-wheeled mobile balancing robots

SK Kim, CK Ahn - IEEE Transactions on Circuits and Systems II …, 2018 - ieeexplore.ieee.org
This brief proposes an outer-loop control mechanism for two-wheeled mobile balancing
robot position-tracking control system applications. The proposed outer-loop controller is …

Reliable low power NoC interconnect

M Vinodhini, NS Murty - Microprocessors and Microsystems, 2018 - Elsevier
Abstract Information communicated through Network on Chip (NoC) in System on Chip
(SoC) is highly prone to different sources of noise, like coupling, radiation and …

Transient error correction coding scheme for reliable low power data link layer in NoC

M Vinodhini, NS Murty, TK Ramesh - IEEE Access, 2020 - ieeexplore.ieee.org
Ensuring reliable data transmission in multicore System on Chip (SoC), which employs
Network on Chip (NoC), is a challenging task. This task is well addressed by Error …

An energy efficient and low overhead fault mitigation technique for internet of thing edge devices reliable on‐chip communication

M Ibrahim, NK Baloch, S Anjum… - Software: Practice …, 2021 - Wiley Online Library
Soft errors in network‐on‐chip (NoC) such as single bit upsets and multibit upsets cause
hazardous effects such as congestion, deadlock, livelock, and corruption of data. Error …

3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs

Z Shirmohammadi, HZ Sabzi… - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
One of the cost-efficient fabrication approaches for connecting layers in three-dimensional
integrated circuits (3D ICs) is the use of through-silicon vias (TSVs). However, the large and …

Joint crosstalk avoidance with multiple bit error correction coding technique for NoC interconnect

TS Teja, TS Kiran, TVVS Narayana… - … on Advances in …, 2018 - ieeexplore.ieee.org
In an On-chip communication where the devices have scaled down to nanometer scale, a
single chip contains numerous processing elements and inter-communication between …

[PDF][PDF] Comparative Reliability Analysis between Horizontal-Vertical-Diagonal Code and Code with Crosstalk Avoidance and Error Correction for NoC Interconnects

HK Abed, WN Flayyih - Journal of Engineering, 2023 - iasj.net
Ensuring reliable data transmission in Network on Chip (NoC) is one of the most challenging
tasks, especially in noisy environments. As crosstalk, interference, and radiation were …

An efficient and low power one-lambda crosstalk avoidance code design for network on chips

Z Shirmohammadi, Z Mahdavi - Microprocessors and Microsystems, 2018 - Elsevier
Crosstalk faults occurring in wires of Networks on Chip (NoCs) can seriously threaten the
reliability of data transfer. One efficient way to tackle crosstalk faults is numeral-based …

Improved asymptotically optimal error correcting codes for avoidance crosstalk type-IV on-chip data buses

M Ajmal, M Ur Rehman, BG Rodrigues - Computational and Applied …, 2023 - Springer
The first memory-less transition bus encoding technique for low power dissipation, crosstalk
avoidance, and error correction simultaneously was presented by Chee et al.(Des Codes …