3D-stacked memory architectures for multi-core processors
GH Loh - ACM SIGARCH computer architecture news, 2008 - dl.acm.org
Three-dimensional integration enables stacking memory directly on top of a microprocessor,
thereby significantly reducing wire delay between the two. Previous studies have examined …
thereby significantly reducing wire delay between the two. Previous studies have examined …
3-D sequential integration: A key enabling technology for heterogeneous co-integration of new function with CMOS
P Batude, T Ernst, J Arcamone, G Arndt… - IEEE Journal on …, 2012 - ieeexplore.ieee.org
3-D sequential integration stands out from other 3-D schemes as it enables the full use of the
third dimension. Indeed, in this approach, 3-D contact density matches with the transistor …
third dimension. Indeed, in this approach, 3-D contact density matches with the transistor …
3-D hyperintegration and packaging technologies for micro-nano systems
JQ Lu - Proceedings of the IEEE, 2009 - ieeexplore.ieee.org
Three-dimensional (3-D) hyperintegration is an emerging technology, which vertically stacks
and interconnects multiple materials, technologies, and functional components to form …
and interconnects multiple materials, technologies, and functional components to form …
[图书][B] Three-dimensional integrated circuit design
Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more
than twice as much new content, adding the latest developments in circuit models …
than twice as much new content, adding the latest developments in circuit models …
Monolithic three dimensional integration of semiconductor integrated circuits
Y Du - US Patent 9,177,890, 2015 - Google Patents
(57) ABSTRACT A three-dimensional integrated circuit comprising top tier nanowire
transistors formed on a bottom tier of CMOS tran sistors, with inter-tier vias, intra-tier vias …
transistors formed on a bottom tier of CMOS tran sistors, with inter-tier vias, intra-tier vias …
3D floorplanning using 2D and 3D blocks
The disclosed embodiments are directed to systems and method for floorplanning an
integrated circuit design using a mix of 2D and 3D blocks that provide a significant …
integrated circuit design using a mix of 2D and 3D blocks that provide a significant …
Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
Y Du - US Patent 9,536,840, 2017 - Google Patents
(57) ABSTRACT A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield
is disclosed. In certain embodiments, at least a graphene layer is positioned between two …
is disclosed. In certain embodiments, at least a graphene layer is positioned between two …
Testing 3D chips containing through-silicon vias
EJ Marinissen, Y Zorian - 2009 International Test Conference, 2009 - ieeexplore.ieee.org
Today's miniaturization and performance requirements result in the usage of high-density
integration and packaging technologies, such as 3D stacked ICs (3D-SICs) based on …
integration and packaging technologies, such as 3D stacked ICs (3D-SICs) based on …
Scale-out processors
Scale-out datacenters mandate high per-server throughput to get the maximum benefit from
the large TCO investment. Emerging applications (eg, data serving and web search) that run …
the large TCO investment. Emerging applications (eg, data serving and web search) that run …
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits
S Bobba, A Chakraborty, O Thomas… - 16th Asia and South …, 2011 - ieeexplore.ieee.org
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential
technology for future gigascale circuits. Since the device layers are processed in sequential …
technology for future gigascale circuits. Since the device layers are processed in sequential …