2022 ICCAD CAD contest problem B: 3D placement with D2D vertical connections
KS Hu, IJ Lin, YH Huang, HY Chi, YH Wu… - Proceedings of the 41st …, 2022 - dl.acm.org
In the chiplet era, the benefits from multiple factors can be observed by splitting a large
single die into multiple small dies. By having the multiple small dies with die-to-die (D2D) …
single die into multiple small dies. By having the multiple small dies with die-to-die (D2D) …
2023 ICCAD CAD Contest Problem B: 3D Placement with Macros
KS Hu, HY Chi, IJ Lin, YH Wu… - 2023 IEEE/ACM …, 2023 - ieeexplore.ieee.org
2023 ICCAD CAD Contest Problem B is an extended problem from 2022 ICCAD CAD
Contest Problem B [1]–[2] for addressing more complex real world 3D implementation …
Contest Problem B [1]–[2] for addressing more complex real world 3D implementation …
Aggressive GPU cache bypassing with monolithic 3D-based NoC
CT Do, CH Kim, SW Chung - The Journal of Supercomputing, 2023 - Springer
Cache bypassing is widely employed to alleviate cache contention and pollution in GPUs.
However, cache bypassing often puts more pressure on the network-on-chip (NoC) since …
However, cache bypassing often puts more pressure on the network-on-chip (NoC) since …
Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits
This paper focuses on iso-on-chip-memory-capacity and iso-footprint Energy-Delay-Product
(EDP) benefits of ultra-dense 3D, eg, monolithic 3D (M3D), computing systems vs …
(EDP) benefits of ultra-dense 3D, eg, monolithic 3D (M3D), computing systems vs …
OO: Optimized One-die Placement for Face-to-face Bonded 3D ICs
The expansion of the IC dimension is ushering in a more-than-Moore era, necessitating
corresponding EDA tools. Existing TSV-based 3D placers focus on minimizing cuts, while …
corresponding EDA tools. Existing TSV-based 3D placers focus on minimizing cuts, while …
Area and Power Optimized RTL to GDS II Flow of a Telecommunication Receiver Core
K Jayasurya, R Ajith… - 2024 5th International …, 2024 - ieeexplore.ieee.org
The Register Transfer Level (RTL) to Graphic Design System II (GDS II) flow is pivotal in any
integrated circuit (IC) design. The work outlines the process of IC design from RTL to GDS II …
integrated circuit (IC) design. The work outlines the process of IC design from RTL to GDS II …
A Multi-Objective Optimization Algorithm Based on Deep Learning for Circuit Partition
Y Cui, Z Xiao, F Wu, K Li - 2023 International Symposium of …, 2023 - ieeexplore.ieee.org
Circuit partition is a critical step during Three-dimensional integrated circuit (3D IC) physical
design. The quality of circuit partition directly affects the subsequent processes (placement …
design. The quality of circuit partition directly affects the subsequent processes (placement …
Sciences de données pour la microélectronique: analyse de topographie
M Kessar - 2021 - theses.hal.science
L'évolution de la technologie pousse la micro-électronique à des contraintes
dimensionnelles de plus en plus restrictives. La taille des transistors diminue constamment …
dimensionnelles de plus en plus restrictives. La taille des transistors diminue constamment …